svt_axi_port_monitor_def_cov_callback Class Reference

covergroup
svt_axi_port_monitor_def_cov_callback::signal_master_slave_valid_ready_dependency

Covergroup: signal_master_slave_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after AWREADY is deasserted, then coverpoint AWVALID_AWREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWVALID_AWREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency) after AWREADY is deasserted.
AWVALID_WREADY_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wready_dependency) after WREADY is deasserted.
AWVALID_RVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rvalid_dependency) after RVALID is deasserted.
AWVALID_BVALID_Dependency : Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bvalid_dependency) after BVALID is deasserted.
WVALID_AWREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awready_dependency) after AWREADY is deasserted.
WVALID_WREADY_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_wready_dependency) after WREADY is deasserted.
WVALID_RVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rvalid_dependency) after RVALID is deasserted.
WVALID_BVALID_Dependency : Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bvalid_dependency) after BVALID is deasserted.
RREADY_AWREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awready_dependency) after AWREADY is deasserted.
RREADY_WREADY_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wready_dependency) after WREADY is deasserted.
RREADY_RVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_rvalid_dependency) after RVALID is deasserted.
RREADY_BVALID_Dependency : Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bvalid_dependency) after BVALID is deasserted.
BREADY_AWREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awready_dependency) after AWREADY is deasserted.
BREADY_WREADY_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wready_dependency) after WREADY is deasserted.
BREADY_RVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rvalid_dependency) after RVALID is deasserted.
BREADY_BVALID_Dependency : Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_bvalid_dependency) after BVALID is deasserted.

covergroup signal_master_slave_valid_ready_dependency @ ( cov_signal_master_slave_dependency_event ) ;
      AWVALID_AWREADY_Dependency : coverpoint cov_awvalid_awready {
      bins AWVALID_and_AWREADY = {1};
      option.at_least = 1;
    }
    AWVALID_WREADY_Dependency : coverpoint cov_awvalid_wready {
      bins AWVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    AWVALID_RVALID_Dependency : coverpoint cov_awvalid_rvalid {
      bins AWVALID_and_RVALID = {1};
      option.at_least = 1;
    }
    AWVALID_BVALID_Dependency : coverpoint cov_awvalid_bvalid {
      bins AWVALID_and_BVALID = {1};
      option.at_least = 1;
    }
    WVALID_AWREADY_Dependency : coverpoint cov_wvalid_awready {
      bins WVALID_and_AWREADY = {1};
      option.at_least = 1;
    }
    WVALID_WREADY_Dependency : coverpoint cov_wvalid_wready {
      bins WVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    WVALID_RVALID_Dependency : coverpoint cov_wvalid_rvalid {
      bins WVALID_and_RVALID = {1};
      option.at_least = 1;
    }
    WVALID_BVALID_Dependency : coverpoint cov_wvalid_bvalid {
      bins WVALID_and_BVALID = {1};
      option.at_least = 1;
    }
     RREADY_AWREADY_Dependency : coverpoint cov_rready_awready {
      bins RREADY_and_AWREADY = {1};
      option.at_least = 1;
    }
    RREADY_WREADY_Dependency : coverpoint cov_rready_wready {
      bins RREADY_and_WREADY = {1};
      option.at_least = 1;
    }
    RREADY_RVALID_Dependency : coverpoint cov_rready_rvalid {
      bins RREADY_and_RVALID = {1};
      option.at_least = 1;
    }
    RREADY_BVALID_Dependency : coverpoint cov_rready_bvalid {
      bins RREADY_and_BVALID = {1};
      option.at_least = 1;
    }
    BREADY_AWREADY_Dependency : coverpoint cov_bready_awready {
      bins BREADY_and_AWREADY = {1};
      option.at_least = 1;
    }
    BREADY_WREADY_Dependency : coverpoint cov_bready_wready {
      bins BREADY_and_WREADY = {1};
      option.at_least = 1;
    }
    BREADY_RVALID_Dependency : coverpoint cov_bready_rvalid {
      bins BREADY_and_RVALID = {1};
      option.at_least = 1;
    }
    BREADY_BVALID_Dependency : coverpoint cov_bready_bvalid {
      bins BREADY_and_BVALID = {1};
      option.at_least = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::signal_master_valid_ready_dependency

Covergroup: signal_master_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWVALID has to remain deasserted for N clocks (user input) after wvalid is deasserted, then coverpoint AWVALID_WVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWVALID_WVALID_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_wvalid_dependency) after WVALID is deasserted.
AWVALID_RREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_rready_dependency) after RREADY is deasserted.
AWVALID_BREADY_Dependency: Will get hit if AWVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awvalid_bready_dependency) after BREADY is deasserted.
WVALID_AWVALID_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_awvalid_dependency) after AWVALID is deasserted.
WVALID_RREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_rready_dependency) after RREADY is deasserted.
WVALID_BREADY_Dependency: Will get hit if WVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wvalid_bready_dependency) after BREADY is deasserted.
RREADY_AWVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_awvalid_dependency) after AWVALID is deasserted.
RREADY_WVALID_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_wvalid_dependency) after WVALID is deasserted.
RREADY_BREADY_Dependency: Will get hit if RREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rready_bready_dependency) after BREADY is deasserted.
BREADY_AWVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_awvalid_dependency) after AWVALID is deasserted.
BREADY_WVALID_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_wvalid_dependency) after WVALID is deasserted.
BREADY_RREADY_Dependency: Will get hit if BREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bready_rready_dependency) after RREADY is deasserted.

covergroup signal_master_valid_ready_dependency @ ( cov_signal_dependency_event ) ;
     AWVALID_WVALID_Dependency : coverpoint cov_awvalid_wvalid {
      bins AWVALID_and_WVALID = {1};
      option.at_least = 1;
    }
    AWVALID_RREADY_Dependency : coverpoint cov_awvalid_rready {
      bins AWVALID_and_RREADY = {1};
      option.at_least = 1;
    }
    AWVALID_BREADY_Dependency : coverpoint cov_awvalid_bready {
      bins AWVALID_and_BREADY = {1};
      option.at_least = 1;
    }
    WVALID_AWVALID_Dependency : coverpoint cov_wvalid_awvalid {
      bins WVALID_and_AWVALID = {1};
      option.at_least = 1;
    }
    WVALID_RREADY_Dependency : coverpoint cov_wvalid_rready {
      bins AWVALID_and_RREADY = {1};
      option.at_least = 1;
    }
    WVALID_BREADY_Dependency : coverpoint cov_wvalid_bready {
      bins WVALID_and_BREADY = {1};
      option.at_least = 1;
    }
    RREADY_AWVALID_Dependency : coverpoint cov_rready_awvalid {
      bins RREADY_and_AWVALID = {1};
      option.at_least = 1;
    }
    RREADY_WVALID_Dependency : coverpoint cov_rready_wvalid {
      bins RREADY_and_WVALID = {1};
      option.at_least = 1;
    }
    RREADY_BREADY_Dependency : coverpoint cov_rready_bready {
      bins RREADY_and_BREADY = {1};
      option.at_least = 1;
    }
    BREADY_AWVALID_Dependency : coverpoint cov_bready_awvalid {
      bins BREADY_and_AWVALID = {1};
      option.at_least = 1;
    }
    BREADY_WVALID_Dependency : coverpoint cov_bready_wvalid {
      bins BREADY_and_WVALID = {1};
      option.at_least = 1;
    }
    BREADY_RREADY_Dependency : coverpoint cov_bready_rready {
      bins BREADY_and_RREADY = {1};
      option.at_least = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::signal_slave_master_valid_ready_dependency

Covergroup: signal_slave_master_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal AWREADY has to remain deasserted for N clocks (user input) after AWVALID is deasserted, then coverpoint AWREADY_AWVALID_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_awvalid_awready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

AWREADY_AWVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_awvalid_dependency) after AWVALIDis deasserted.
AWREADY_WVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_wvalid_dependency) after WVALID is deasserted.
AWREADY_RVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_rvalid_dependency) after RVALID is deasserted.
AWREADY_BVALID_Dependency : Will get hit if AWREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_awready_and_bvalid_dependency) after BVALID is deasserted.
WREADY_AWVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_awvalid_dependency) after AWVALID is deasserted.
WREADY_WVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_wvalid_dependency) after WVALID is deasserted.
WREADY_RREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_rready_dependency) after RREADY is deasserted.
WREADY_BREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_and_bready_dependency) after BREADY is deasserted.
RVALID_AWREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_awready_dependency) after AWREADY is deasserted.
RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_wready_dependency) after WREADY is deasserted.
RVALID_RREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_rready_dependency) after RREADY is deasserted.
RVALID_BREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_and_bready_dependency) after BREADY is deasserted.
BVALID_AWREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_awready_dependency) afterAWREADY is deasserted.
BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_wready_dependency) after WREADY is deasserted.
BVALID_RREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_rready_dependency) after RREADY is deasserted.
BVALID_BREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_and_bready_dependency) after BREADY is deasserted.

covergroup signal_slave_master_valid_ready_dependency @ ( cov_signal_slave_master_dependency_event ) ;
      AWREADY_AWVALID_Dependency : coverpoint cov_awready_and_awvalid {
      bins AWREADY_and_AWVALID = {1};
      option.at_least = 1;
    }
    AWREADY_WVALID_Dependency : coverpoint cov_awready_and_wvalid {
      bins AWREADY_and_WVALID = {1};
      option.at_least = 1;
    }
    AWREADY_RVALID_Dependency : coverpoint cov_awready_and_rvalid {
      bins AWREADY_and_RVALID = {1};
      option.at_least = 1;
    }
    AWREADY_BVALID_Dependency : coverpoint cov_awready_and_bvalid {
      bins AWREADY_and_BVALID = {1};
      option.at_least = 1;
    }
    WREADY_AWVALID_Dependency : coverpoint cov_wready_and_awvalid {
      bins WREADY_and_AWVALID = {1};
      option.at_least = 1;
    }
    WREADY_WVALID_Dependency : coverpoint cov_wready_and_wvalid {
      bins WREADY_and_WVALID = {1};
      option.at_least = 1;
    }
    WREADY_RREADY_Dependency : coverpoint cov_wready_and_rready {
      bins WREADY_and_RREADY = {1};
      option.at_least = 1;
    }
    WREADY_BREADY_Dependency : coverpoint cov_wready_and_bready {
      bins WREADY_and_BREADY = {1};
      option.at_least = 1;
    }
     RVALID_AWREADY_Dependency : coverpoint cov_rvalid_and_awready {
      bins RVALID_and_AWREADY = {1};
      option.at_least = 1;
    }
    RVALID_WREADY_Dependency : coverpoint cov_rvalid_and_wready {
      bins RVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    RVALID_RREADY_Dependency : coverpoint cov_rvalid_and_rready {
      bins RVALID_and_RREADY = {1};
      option.at_least = 1;
    }
    RVALID_BREADY_Dependency : coverpoint cov_rvalid_and_bready {
      bins RVALID_and_BREADY = {1};
      option.at_least = 1;
    }
    BVALID_AWREADY_Dependency : coverpoint cov_bvalid_and_awready {
      bins BVALID_and_AWREADY = {1};
      option.at_least = 1;
    }
    BVALID_WREADY_Dependency : coverpoint cov_bvalid_and_wready {
      bins BVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    BVALID_RREADY_Dependency : coverpoint cov_bvalid_and_rready {
      bins BVALID_and_RREADY = {1};
      option.at_least = 1;
    }
    BVALID_BREADY_Dependency : coverpoint cov_bvalid_and_bready {
      bins BVALID_and_BREADY = {1};
      option.at_least = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::signal_slave_valid_ready_dependency

Covergroup: signal_slave_valid_ready_dependency

The bins will get hit if signals are deassarted for N clock cycle mentioned by the user using port configuration parameter. For Eg: The signal WREADY has to remain deasserted for N clocks (user input) after arready is deasserted, then coverpoint WREADY_ARREADY_Dependency will get hit. In this case N value will be svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency. It is constructed when port_kind is AXI_MASTER or AXI_SLAVE & valid_ready_dependency_coverage_enable is set to 1.

Coverpoints:

WREADY_ARREADY_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_arready_dependency) after ARREADY is deasserted.
WREADY_RVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_rvalid_dependency) after RVALID is deasserted.
WREADY_BVALID_Dependency : Will get hit if WREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_wready_bvalid_dependency) after BVALID is deasserted.
ARREADY_WREADY_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_wready_dependency) after WREADY is deasserted.
ARREADY_RVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_rvalid_dependency) after RVALID is deasserted.
ARREADY_BVALID_Dependency : Will get hit if ARREADY remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_arready_bvalid_dependency) after BVALID is deasserted.
RVALID_ARREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_arready_dependency) after ARREADY is deasserted.
RVALID_WREADY_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_wready_dependency) after WREADY is deasserted.
RVALID_BVALID_Dependency : Will get hit if RVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_rvalid_bvalid_dependency) after BVALID is deasserted.
BVALID_ARREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_arready_dependency) after ARREADY is deasserted.
BVALID_WREADY_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_wready_dependency) after WREADY is deasserted.
BVALID_RVALID_Dependency : Will get hit if BVALID remains deasserted for N clock cycles(N = svt_axi_port_configuration :: cov_num_clks_bvalid_rvalid_dependency) after RVALID is deasserted.

covergroup signal_slave_valid_ready_dependency @ ( cov_signal_slave_dependency_event ) ;
      WREADY_ARREADY_Dependency : coverpoint cov_wready_arready {
      bins WREADY_and_ARREADY = {1};
      option.at_least = 1;
    }
    WREADY_RVALID_Dependency : coverpoint cov_wready_rvalid {
      bins WREADY_and_RVALID = {1};
      option.at_least = 1;
    }
    WREADY_BVALID_Dependency : coverpoint cov_wready_bvalid {
      bins WREADY_and_BVALID = {1};
      option.at_least = 1;
    }
    ARREADY_WREADY_Dependency : coverpoint cov_arready_wready {
      bins ARREADY_and_WREADY = {1};
      option.at_least = 1;
    }
    ARREADY_RVALID_Dependency : coverpoint cov_arready_rvalid{
      bins ARREADY_and_RVALID = {1};
      option.at_least = 1;
    }
    ARREADY_BVALID_Dependency : coverpoint cov_arready_bvalid {
      bins ARREADY_and_BVALID = {1};
      option.at_least = 1;
    }
    RVALID_ARREADY_Dependency : coverpoint cov_rvalid_arready {
      bins RVALID_and_ARREADY = {1};
      option.at_least = 1;
    }
    RVALID_WREADY_Dependency : coverpoint cov_rvalid_wready {
      bins RVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    RVALID_BVALID_Dependency : coverpoint cov_rvalid_bvalid {
      bins RVALID_and_BVALID = {1};
      option.at_least = 1;
    }
    BVALID_ARREADY_Dependency : coverpoint cov_bvalid_arready {
      bins BVALID_and_ARREADY = {1};
      option.at_least = 1;
    }
    BVALID_WREADY_Dependency : coverpoint cov_bvalid_wready {
      bins BVALID_and_WREADY = {1};
      option.at_least = 1;
    }
    BVALID_RVALID_Dependency : coverpoint cov_bvalid_rvalid {
      bins BVALID_and_RVALID = {1};
      option.at_least = 1;
    }
         option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_barrier_outstanding_xact_ace

Covergroup: trans_ace_barrier_outstanding_xact_ace

This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE and trans_ace_barrier_outstanding_xact_enable & barrier enable set to 1.

Coverpoints:

barrier_outstanding_xact : Captures total number of read and write barrier outstanding transactions. When svt_axi_port_configuration :: axi_interface_type is configured as AXI_ACE maximum number of 256 outstanding transactions is tracked. When svt_axi_port_configuration :: axi_interface_type is configured as ACE_LITE, outstanding transactions greater than 256 are also tracked. This is as per section C8.4.1 of AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613"

covergroup trans_ace_barrier_outstanding_xact_ace @ ( cov_barrier_outstanding_event_ace ) ;
      barrier_outstanding_xact : coverpoint num_outstanding_xact iff(barrier_outstanding_xact_flag){
    bins barrier_outstanding_xact_range_low = {[1:32]};
    bins barrier_outstanding_xact_range_med = {[33:128]};
    bins barrier_outstanding_xact_range_max = {[129:256]};
    ignore_bins barrier_outstanding_xact_range_above_256 = {257};
    option.weight = 1;
    type_option.weight = 1;
  }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_barrier_outstanding_xact_acelite

Covergroup: trans_ace_barrier_outstanding_xact_acelite

This Covergroup captures barrier outstanding transaction. It is constructed when interface type is ACE_LITE and trans_ace_barrier_outstanding_xact_enable & barrier enable set to 1.

Coverpoints:

covergroup trans_ace_barrier_outstanding_xact_acelite @ ( cov_barrier_outstanding_event_acelite ) ;
      barrier_outstanding_xact : coverpoint num_outstanding_xact iff(barrier_outstanding_xact_flag){
    bins barrier_outstanding_xact_range_low = {[1:32]};
    bins barrier_outstanding_xact_range_med = {[33:128]};
    bins barrier_outstanding_xact_range_max = {[129:256]};
    bins barrier_outstanding_xact_range_above_256 = {257};
    option.weight = 1;
    type_option.weight = 1;
  }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp

Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that * generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port :Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 1;
    type_option.weight = 1;
   }
     snoop_xact_type : coverpoint master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 1;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101};
       // ignoring snoop_responses where is_shared bit is asserted for READUNIQUE transactions
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::READUNIQUE} &&
                                                 binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b1101,4'b1000,4'b1001};
       ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite

Covergroup: trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with non overlapping address The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite is applicable only for ACE Masters .The covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master .This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_non_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 1;
    type_option.weight = 1;
   }
     snoop_xact_type : coverpoint master_snoop_xact_type {
       bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
       bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
       bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
       bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
       option.weight = 1;
    }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 1;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101};
        ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_arsnoop_acsnoop

Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for all snoop transactions recieved on master port . This excludes DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Two ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_overlapping_arsnoop_acsnoop;
      coherent_read_xact_type : coverpoint master_coherent_xact_type {
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_xact_type : coverpoint master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_read_xact_type{
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite

Covergroup: trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_read_xact_type:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on read channel of master . This excludes READNOSNOOP,DVMMESSAGE,DVMCOMPLETE,READBARRIER transactions The bins in this covergroup will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address Atleast one ACE and one ACE_LITE master needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_overlapping_arsnoop_acsnoop_one_ace_acelite;
      coherent_read_xact_type : coverpoint master_coherent_xact_type {
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
            snoop_xact_type : coverpoint master_snoop_xact_type {
       bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
       bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
       bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
       bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
       option.weight = 1;
    }
    ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_read_xact_type{
       option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled is applicable only for ACE Masters.The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled needs at least one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_disabled;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 1;
    type_option.weight = 1;
   }
    snoop_xact_type : coverpoint master_snoop_xact_type {
       bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
       bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
       bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
       bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
       option.weight = 1;
    }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 1;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101,4'b0001};
        ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_evict = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::EVICT} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1001,4'b1101,4'b1000};
        option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled

This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled is applicable only for ACE Masters. The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled needs atleast one ACE and one ACE_LITE master in the system. It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Coverpoints: snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions coherent_write_xact_type_generate_snoop:Coverpoint of svt_axi_transaction :: coherent_xact_type for all coherent transactions initiated on write channel of master. This coverpoint includes only those transactions that generate snoop.This includes WRITEUNIQUE and WRITELINEUNIQUE transactions snoop_crresp_on_ace_port : Coverpoint of cresp.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enabled;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 1;
    type_option.weight = 1;
   }
            snoop_xact_type : coverpoint master_snoop_xact_type {
       bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
       bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
       bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
       bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
       option.weight = 1;
    }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 1;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101,4'b0001};
        ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_evict = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::EVICT} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1001,4'b1101,4'b1000};
        option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_one_ace_acelite_writeevict_enable

The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER and interface_category is not AXI_READ_ONLY.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_disabled;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 1;
    type_option.weight = 1;
   }
     snoop_xact_type : coverpoint master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 0;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101,4'b0001};
       // ignoring snoop_responses where is_shared bit is asserted for READUNIQUE transactions
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::READUNIQUE} &&
                                                 binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b1101,4'b1000,4'b1001};
       // Ignoring the below ignore_bins for writeback and writeclean transactions as mastercan invalidate the snoop responses
               ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_evict = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::EVICT} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1001,4'b1101,4'b1000};
         option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled

Covergroup: trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled

The bins in covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled will be hit when a coherent transaction is outstanding while a snoop transaction is outstanding on same port with overlapping address The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled is applicable only for ACE Masters .The covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled needs at least two ACE masters in the system . It is constructed and sampled when interface_type is AXI_ACE or port_kind is AXI_MASTER.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.6.2

covergroup trans_ace_concurrent_overlapping_awsnoop_acsnoop_crresp_writeevict_enabled;
      coherent_write_xact_type_gen_snoop : coverpoint coherent_write_xact_type_generate_snoop {
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 1;
    type_option.weight = 1;
   }
     snoop_xact_type : coverpoint master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
            snoop_crresp_on_ace_port: coverpoint snoop_resp_ace_master[3:0] {
       bins cresp_0000 = {4'b0000};
       bins cresp_1000 = {4'b1000};
       bins cresp_0001 = {4'b0001};
       bins cresp_1001 = {4'b1001};
       bins cresp_0101 = {4'b0101};
       bins cresp_1101 = {4'b1101};
       option.weight = 1;
    }
    snoop_crresp_wu : coverpoint snoop_resp_ace_master[4] {
       bins cresp_wasunique = {1'b1};
       bins cresp_wasnotunique = {1'b0};
       option.weight = 1;
    }
     ace_concurrent_overlap_snoop_xact : cross snoop_xact_type,coherent_write_xact_type_gen_snoop,snoop_crresp_on_ace_port,snoop_crresp_wu{
       // Ignoring snoop_responses where is_shared is asserted and where data_transfer is asserted as recommended behaviour for MAKEINVALID is not tot transfer data
       ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000 };
       // Ignoring snoop_responses where is_shared bit is asserted or where data_transfer is asserted and pass_dirty is deasserted as CLEANINVALID will transfer data only when pass_dirty is asserted
       ignore_bins ignore_invalid_rresp_ud_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b0000,4'b0101,4'b0001};
       // ignoring snoop_responses where is_shared bit is asserted for READUNIQUE transactions
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(snoop_xact_type) intersect {
                                                   svt_axi_snoop_transaction::READUNIQUE} &&
                                                 binsof(snoop_crresp_on_ace_port) intersect {
                                                   4'b1101,4'b1000,4'b1001};
       // Ignoring the below ignore_bins for writeback and writeclean transactions as mastercan invalidate the snoop responses
               ignore_bins ignore_invalid_snoop_crresp_writeunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_writelineunique = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::WRITELINEUNIQUE} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1101};
       ignore_bins ignore_invalid_snoop_crresp_evict = binsof(coherent_write_xact_type_gen_snoop) intersect {svt_axi_transaction::EVICT} &&
                                                           binsof(snoop_crresp_on_ace_port) intersect {
                                                           4'b0101,4'b1001,4'b1101,4'b1000};
        option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid: The number of bins will be equal to the programmed value of User-defined macron SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. If user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8.
Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

covergroup trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid(int num_outstanding_xact);
     num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid: coverpoint num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid {
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid[] = {[1:num_outstanding_xact]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range: This will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is
Example: If id_wdith is 7 then num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0 [0 : 15] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_1 [16 : 31] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_2 [32 : 47] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_3 [48 : 63] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_4 [64 : 79] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_5 [80 : 95] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_6 [96 : 111] num_outstanding_dvm_tlb_invalidate_xact_with_diff_arid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

covergroup trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range(int id_width);
     num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range: coverpoint num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range {
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_0 = {[0:id_width-1]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_1 = {[(id_width):((2*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_2 = {[(2*id_width):((3*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_3 = {[(3*id_width):((4*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_4 = {[(4*id_width):((5*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_5 = {[(5*id_width):((6*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_6 = {[(6*id_width):((7*id_width)-1)]};
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_diff_arid_range_7 = {[(7*id_width):((8*id_width)-1)]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

Covergroup: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid

This covergroup captures the number of outstanding transactions with DVM TLBI requests with a matching ARID. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid_enable = 1 Configured value of svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_read_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.

Coverpoints:

num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid: The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_dvm_tlbi_num_outstanding_xacts and the default value of which is 64.
Example: If outstanding DVM TLBI transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_dvm_tlbi_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding DVM TLBI transactions matching with ARID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

covergroup trans_ace_num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid(int num_outstanding_xact);
     num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid: coverpoint num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid {
      bins num_outstanding_dvm_tlb_invalidate_xacts_with_same_arid[] = {[1:num_outstanding_xact]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ace_num_outstanding_snoop_xacts

Covergroup: trans_ace_num_outstanding_snoop_xacts

It is constructed and sampled when interface_type is AXI_ACE and trans_ace_num_outstanding_snoop_xacts_enable set to 1.

Coverpoints:

num_outstanding_snoop_xacts: Captures the number of outstanding snoop transactions.The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_snoop_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_snoop_xact which indicates the number of outstanding snoop transactions VIP can support.
Applicable only for master and when svt_axi_port_configuration :: axi_interface_type is ACE.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5

covergroup trans_ace_num_outstanding_snoop_xacts(int num_outstanding_xact);
     num_outstanding_snoop_xacts: coverpoint num_outstanding_snoop_xacts{
      bins num_outstanding_snoop_xacts[] = {[1:num_outstanding_xact]} ;
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_ar_aw_stalled_for_ac_channel

Covergroup: trans_ar_aw_stalled_for_ac_channel

This Covergroup captures stalled read and write transaction y interconnect when request is issued from master. It is constructed when interface_type is AXI_ACE & interface_category is AXI_READ_WRITE and trans_ar_aw_stalled_for_ac_channel_enable set to 1.

Coverpoints:

axi_ar_aw_stalled_for_ac_channel: This is covered when read transaction on AR channel OR WriteUnique/WriteLineUnique transactions on AW channel from a master are stalled by interconnect, while waiting for the snoop response from the same master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

covergroup trans_ar_aw_stalled_for_ac_channel @ ( cov_ar_aw_stalled_for_ac_channel_sample_event ) ;
     axi_ar_aw_stalled_for_ac_channel: coverpoint ar_aw_stalled_for_ac_channel {
      bins readonce_stalled_for_snoop = {1};
      bins readshared_stalled_for_snoop = {2};
      bins readclean_stalled_for_snoop = {3};
      bins readnotshareddirty_stalled_for_snoop = {4};
      bins readunique_stalled_for_snoop = {5};
      bins cleanunique_stalled_for_snoop = {6};
      bins makeunique_stalled_for_snoop = {7};
      bins cleanshared_stalled_for_snoop = {8};
      bins cleaninvalid_stalled_for_snoop = {9};
      bins makeinvalid_stalled_for_snoop = {10};
        bins cleansharedpersist_stalled_for_snoop = {14};
      bins writeunique_stalled_for_snoop = {15};
      bins writelineunique_stalled_for_snoop = {16};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi4_stream_delay

Covergroup: trans_meta_axi_read

This Covergroup captures delay scenarios for tvalid signal for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_axi4_stream_delay_enable is asserted.

Coverpoints:

TVALID_Delay: Captures min, mid and max range of delay signal tvalid
TREADY_Delay: Captures min, mid and max range of delay signal tready

covergroup trans_axi4_stream_delay;
     option.per_instance = 1;
    TVALID_Delay : coverpoint cov_TVALID_Delay {
      bins tvalid_delay_min = {0};
      bins tvalid_delay_mid = {[1:( 16/2)]};
      bins tvalid_delay_max = {[( 16/2)+1:$]};
    }
    TREADY_Delay : coverpoint cov_TREADY_Delay {
      bins tready_delay_min = {0};
      bins tready_delay_mid = {[1:( 16/2)]};
      bins tready_delay_max = {[( 16/2)+1:$]};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_awakeup

Covergroup: trans_axi_awakeup

This Covergroup captures wakeup and valid signal delay scenario . It is constructed when acwakeup_enable is set to 1 and port_kind is AXI_MASTER.

Coverpoints:

AWAKEUP_before_ARVALID_Delay: Captures min, mid and max range of delays between signals awakeup to arvalid
AWAKEUP_after_ARVALID_Delay: Captures min, mid and max range of delays between signals arvalid to awakeup
AWAKEUP_ARVALID_same_time: Captures delays of signals awakeup and arvalid assertion same time
AWAKEUP_to_prev_AWAKEUP_Delay: Captures min, mid and max range of delays between signals awakeup to previous awakeup

covergroup trans_axi_awakeup @ ( cov_awakeup_sample_event ) ;
      option.per_instance = 1;
    AWAKEUP_before_ARVALID_Delay : coverpoint cov_AWAKEUP_before_ARVALID_Delay {
      bins awakeup_before_arvalid_min = { 0};
      bins awakeup_before_arvalid_mid = {[`SVT_AXI_MIN_AWAKEUP_ASSERT_DELAY+1:( 6/2)]};
      bins awakeup_before_arvalid_max = {[( 6/2)+1: 6]};
    }
    AWAKEUP_after_ARVALID_Delay : coverpoint cov_AWAKEUP_after_ARVALID_Delay {
      bins awakeup_after_arvalid_min = { 0};
      bins awakeup_after_arvalid_mid = {[`SVT_AXI_MIN_AWAKEUP_ASSERT_DELAY+1:( 6/2)]};
      bins awakeup_after_arvalid_max = {[( 6/2)+1: 6]};
    }
    AWAKEUP_ARVALID_same_time : coverpoint cov_AWAKEUP_ARVALID_same_time {
      bins awakeup_arvalid_same_time = {0};
    }
     AWAKEUP_to_prev_AWAKEUP_Delay : coverpoint cov_AWAKEUP_to_prev_AWAKEUP_Delay {
      bins awakeup_to_prev_awakeup_delay_min = {2};
   // bins awakeup_to_prev_awakeup_delay_mid = {[3:((`SVT_AXI_MAX_ARVALID_DELAY + `SVT_AXI_MAX_ARREADY_DELAY + `SVT_AXI_MAX_AWAKEUP_ASSERT_DELAY)/3)]};
   // bins awakeup_to_prev_awakeup_delay_max = {[((`SVT_AXI_MAX_ARVALID_DELAY + `SVT_AXI_MAX_ARREADY_DELAY + `SVT_AXI_MAX_AWAKEUP_ASSERT_DELAY)/3)+1:$]};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_diff_arid

Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_enable & id_width set to 1 and cov_num_outstanding_xacts_range_enable set to 0.

Coverpoints:

read_outstanding_xacts_with_diff_arid: Captures the number of outstanding read transactions with different ARID value. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for ARID width greater than 8
If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID2 ARID3 ARID4 ARID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with ARID1,ARID2 ARID3 ARID4 ARID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique ARID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique ARID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_diff_arid(int num_outstanding_xact);
     read_outstanding_xacts_with_diff_arid: coverpoint read_outstanding_xacts_with_diff_arid{
      bins read_outstanding_xacts_with_diff_arid[] = {[1:num_outstanding_xact]} ;
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_diff_arid_range

Covergroup: trans_axi_num_outstanding_xacts_with_diff_arid_range

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_arid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 and read_chan_id_width >=3.

Coverpoints:

read_outstanding_xacts_with_diff_arid_range: This cover group captures the range of arid values of outstanding read transactions. This covergroup will construct eight different bins to cover all the possible ranges of arid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If id_wdith is 7 then read_outstanding_xacts_with_diff_arid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
read_outstanding_xacts_with_diff_arid_range_0 [0 : 15] read_outstanding_xacts_with_diff_arid_range_1 [16 : 31] read_outstanding_xacts_with_diff_arid_range_2 [32 : 47] read_outstanding_xacts_with_diff_arid_range_3 [48 : 63] read_outstanding_xacts_with_diff_arid_range_4 [64 : 79] read_outstanding_xacts_with_diff_arid_range_5 [80 : 95] read_outstanding_xacts_with_diff_arid_range_6 [96 : 111] read_outstanding_xacts_with_diff_arid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_diff_arid_range(int id_width);
     read_outstanding_xacts_with_diff_arid_range: coverpoint read_outstanding_xacts_with_diff_arid_range{
      bins read_outstanding_xacts_with_diff_arid_range_0 = {[0:(id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_1 = {[(id_width):(2*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_2 = {[(2*id_width):(3*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_3 = {[(3*id_width):(4*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_4 = {[(4*id_width):(5*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_5 = {[(5*id_width):(6*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_6 = {[(6*id_width):(7*id_width-1)]};
      bins read_outstanding_xacts_with_diff_arid_range_7 = {[(7*id_width):(8*id_width-1)]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_diff_awid

Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and id_width is not 0.

Coverpoints:

write_outstanding_xacts_with_diff_awid: Captures the number of outstanding write transactions with different AWID. The number of bins will be equal to the programmed value of User-defined macro SVT_AXI_NUM_BINS_FOR_ID_WIDTH_GREATER_THAN_EIGHT which has a default value of 256. So, if user does not override this macro then this covergroup will create 256 bins for AWID width greater than 8
If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: write_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example:
If outstanding transactions have the following IDs: AWID1 AWID1 AWID2 AWID3 AWID4 AWID5. The bins hit will be 1,2,3,4,5 (for outstanding transactions with AWID1,AWID2 AWID3 AWID4 AWID5) The coverage is a continuous logic. If there is only one outstanding transaction in the queue with unique AWID value, the bin 1 will get hit. Subsequently as and when new outstanding transactions comes with unique AWID values further bins will keep getting hit.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_diff_awid(int num_outstanding_xact);
     write_outstanding_xacts_with_diff_awid: coverpoint write_outstanding_xacts_with_diff_awid{
      bins write_outstanding_xacts_with_diff_awid[] = {[1:num_outstanding_xact]} ;
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_diff_awid_range

Covergroup: trans_axi_num_outstanding_xacts_with_diff_awid_range

It is constructed and sampled when trans_axi_num_outstanding_xacts_with_diff_awid_range_enable & cov_num_outstanding_xacts_range_enable set to 1 ,num_outstanding_xacts is not -1 and write_chan_id_width >= 3.

Coverpoints:

write_outstanding_xacts_with_diff_awid_range: This cover group captures the range of awid values of outstanding write transactions. This covergroup will construct eight different bins to cover all the possible ranges of awid. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 1 then svt_axi_port_configuration :: read_chan_id_width is considered for creation of bins. If svt_axi_port_configuration :: use_separate_rd_wr_chan_id_width is programmed to 0 then svt_axi_port_configuration :: id_width is considered for creation of bins.
Example: If id_wdith is 7 then write_outstanding_xacts_with_diff_awid_range can be 0 to 127 and that will be cover under defined 8 bins as follows.
write_outstanding_xacts_with_diff_awid_range_0 [0 : 15] write_outstanding_xacts_with_diff_awid_range_1 [16 : 31] write_outstanding_xacts_with_diff_awid_range_2 [32 : 47] write_outstanding_xacts_with_diff_awid_range_3 [48 : 63] write_outstanding_xacts_with_diff_awid_range_4 [64 : 79] write_outstanding_xacts_with_diff_awid_range_5 [80 : 95] write_outstanding_xacts_with_diff_awid_range_6 [96 : 111] write_outstanding_xacts_with_diff_awid_range_7 [112 : 127]

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_diff_awid_range(int id_width);
     write_outstanding_xacts_with_diff_awid_range: coverpoint write_outstanding_xacts_with_diff_awid_range{
      bins write_outstanding_xacts_with_diff_awid_range_0 = {[0:id_width-1]};
      bins write_outstanding_xacts_with_diff_awid_range_1 = {[(id_width):(2*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_2 = {[(2*id_width):(3*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_3 = {[(3*id_width):(4*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_4 = {[(4*id_width):(5*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_5 = {[(5*id_width):(6*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_6 = {[(6*id_width):(7*id_width-1)]};
      bins write_outstanding_xacts_with_diff_awid_range_7 = {[(7*id_width):(8*id_width-1)]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_multiple_same_arid

Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_arid

This covergroup captures the number of outstanding read transactions with same ARID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids ARID1, ARID2 and ARID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with ARID1,then bins read_same_arid_1, read_outstanding_xacts_with_same_arid_1 to read_outstanding_xacts_with_same_arid_50 will get hit. It is constructed and sampled when interface_category is not AXI_WRITE_ONLY and num_outstanding_xact is not -1 & trans_axi_num_outstanding_xacts_with_multiple_same_arid_enable set to 1.

Coverpoints:

read_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids
num_outstanding_read : Captures number of outstanding read transactions with a matching ARID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = ARID1, cov_multi_same_ids[1] = ARID2, cov_multi_same_ids[1] = ARID3 and outstanding transactions have the following IDs: ARID1 ARID2 ARID1 ARID4 ARID3 ARID1 ARID3 ARID5 ARID2. The bins of read_outstanding_same_id hit will be read_same_arid_1,read_same_arid_2 and read_same_arid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be read_same_arid_1 with read_outstanding_xacts_3,read_same_arid_2 with read_outstanding_xacts_2, read_same_arid_3 with read_outstanding_xacts_1 as there are 3 outstanding transactions matching with ARID1, 2 outstanding transactions with ARID2 and 1 outstanding transaction with ARID3.

Cross Coverpoints :

cross_same_id_with_num_outstanding_xacts: Crosses coverpoints read_outstanding_same_id and num_outstanding_read

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_multiple_same_arid(int num_same_ids, int num_outstanding_xact);
          read_outstanding_same_id : coverpoint cov_read_same_id {
      bins read_same_arid[] = {[1:num_same_ids]};
      option.weight = 1;
    }
    num_outstanding_read : coverpoint cov_num_read_outstanding_same_arid{
      bins read_outstanding_xacts[] = {[1:num_outstanding_xact]};
      option.weight = 1;
    }
         cross_same_id_with_num_outstanding_xacts : cross read_outstanding_same_id, num_outstanding_read {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_multiple_same_awid

Covergroup: trans_axi_num_outstanding_xacts_with_multiple_same_awid

This covergroup captures the number of outstanding write transactions with same AWID values which is in progress, if master is programmed with multiple same ids. For Example : If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], then the master will have three different ids AWID1, AWID2 and AWID3.This covergroup will cross all the 3 ids with svt_axi_port_configuration :: num_outstanding_xact. If number of outstanding transactions are 50 with AWID1,then bins write_same_awid_1, write_outstanding_xacts_with_same_awid_1 to write_outstanding_xacts_with_same_awid_50 will get hit. It is constructed and sampled when trans_axi_num_outstanding_xacts_with_multiple_same_awid_enable set to 1 & num_outstanding_xacts is not -1.

Coverpoints:

write_outstanding_same_id: Captures the same id values programmed in svt_axi_port_configuration :: cov_multi_same_ids
num_outstanding_write : Captures number of outstanding write transactions with a matching AWID values to the one programmed in svt_axi_port_configuration :: cov_multi_same_ids.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If a master is programmed with svt_axi_port_configuration :: cov_multi_same_ids = new[3], cov_multi_same_ids[0] = AWID1, cov_multi_same_ids[1] = AWID2, cov_multi_same_ids[1] = AWID3 and outstanding transactions have the following IDs: AWID1 AWID2 AWID1 AWID4 AWID3 AWID1 AWID3 AWID5 AWID2. The bins of write_outstanding_same_id hit will be write_same_awid_1,write_same_awid_2 and write_same_awid_3, bins of cross_same_id_with_num_outstanding_xacts hit will be write_same_awid_1 with write_outstanding_xacts_3,write_same_awid_2 with write_outstanding_xacts_2, write_same_awid_3 with write_outstanding_xacts_1 as there are 3 outstanding transactions matching with AWID1, 2 outstanding transactions with AWID2 and 1 outstanding transaction with AWID3.

Cross Coverpoints :

cross_same_id_with_num_outstanding_xacts: Crosses Coverpoints write_outstanding_same_id, num_outstanding_write .

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_multiple_same_awid(int num_same_ids, int num_outstanding_xact);
          write_outstanding_same_id : coverpoint cov_write_same_id {
      bins write_same_awid[] = {[1:num_same_ids]};
      option.weight = 1;
    }
    num_outstanding_write : coverpoint cov_num_write_outstanding_same_awid{
      bins write_outstanding_xacts[] = {[1:num_outstanding_xact]};
      option.weight = 1;
    }
         cross_same_id_with_num_outstanding_xacts : cross write_outstanding_same_id, num_outstanding_write {
     option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_same_arid

Covergroup: trans_axi_num_outstanding_xacts_with_same_arid

It is constructed and sampled when interface_ category is not AXI_WRITE_ONLY and trans_axi_num_outstanding_xacts_with_same_arid_enable set to 1 & num_outstanding_xact is not -1.

Coverpoints:

read_outstanding_xacts_with_same_arid: Captures the number of outstanding read transactions with a matching ARID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If outstanding transactions have the following IDs: ARID1 ARID1 ARID3 ARID1 ARID3 ARID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to ARID1. The bins hit will be 1,2 and 3 as there are 3 outstanding transactions matching with ARID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_same_arid(int num_outstanding_xact);
     read_outstanding_xacts_with_same_arid: coverpoint read_outstanding_xacts_with_same_arid{
      bins read_outstanding_xacts_with_same_arid[] = {[1:num_outstanding_xact]} ;
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_num_outstanding_xacts_with_same_awid

Covergroup: trans_axi_num_outstanding_xacts_with_same_awid

It is constructed and sampled when interface_category is not AXI_READ_ONLY and trans_axi_num_outstanding_xacts_with_same_awid_enable set to 1 & num_outstanding_xacts is not -1.

Coverpoints:

write_outstanding_xacts_with_same_awid: Captures the number of outstanding write transactions with a matching AWID value to the one programmed in svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts.
The number of bins for this coverpoint is controlled by svt_axi_port_configuration :: cov_bins_num_outstanding_xacts, the default value of which is 64. Configured value of svt_axi_port_configuration :: cov_bins_num_outstanding_xacts should be less than or equal to configured value of svt_axi_port_configuration :: num_outstanding_xact or svt_axi_port_configuration :: num_write_outstanding_xact if svt_axi_port_configuration :: num_outstanding_xact is set to -1 which indicates the number of outstanding transactions VIP can support.
Example: If outstanding transactions have the following IDs: AWID1 AWID1 AWID3 AWID1 AWID3 AWID2 and svt_axi_port_configuration :: cov_same_id_in_outstanding_xacts is programmed to AWID1. The bins hit will be 1, 2 and 3 as there are 3 outstanding transactions matching with AWID1.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A5.2

covergroup trans_axi_num_outstanding_xacts_with_same_awid(int num_outstanding_xact);
     write_outstanding_xacts_with_same_awid: coverpoint write_outstanding_xacts_with_same_awid{
      bins write_outstanding_xacts_with_same_awid[] = {[1:num_outstanding_xact]} ;
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_read_handshake_delay

Covergroup: trans_axi_read_handshake_delay

This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for read address and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY.

Coverpoints:

last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay:Captures min, mid and max range of delays between last arvalid_arready handshake to the next arvalid_arready handshake
last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arvalid
last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay: Captures min,mid and max range of delays between last arvalid_arready handshake to the next arready
last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay: Captures min,mid and max range of delays between last arready to the next arvalid_arready handshake
last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay:Captures min, mid and max range of delays between last rvalid_rready handshake to the next rvalid_rready handshake
last_RVALID_RREADY_handshake_to_next_RVALID_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rvalid
last_RVALID_RREADY_handshake_to_next_RREADY_Delay: Captures min,mid and max range of delays between last rvalid_rready handshake to the next rready
last_RREADY_to_next_RVALID_RREADY_handshake_Delay: Captures min,mid and max range of delays between last rready to the next rvalid_rready handshake
last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last rvalid_rready data beat handshake to the next rvalid_rready data beat handshake

covergroup trans_axi_read_handshake_delay;
     option.per_instance = 1;
    last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay : coverpoint cov_last_ARVALID_ARREADY_handshake_to_next_ARVALID_ARREADY_handshake_Delay {
      bins last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_min = {1};
      bins last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_arvalid_arready_handshake_to_next_arvalid_arready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    last_ARVALID_ARREADY_handshake_to_next_ARVALID_Delay : coverpoint cov_prev_handshake_ARVALID_Delay {
      bins last_arvalid_arready_handshake_to_next_arvalid_delay_min = {1};
      bins last_arvalid_arready_handshake_to_next_arvalid_delay_mid = {[2:( 16/2)]};
      bins last_arvalid_arready_handshake_to_next_arvalid_delay_max = {[( 16/2)+1:$]};
    }
    last_ARVALID_ARREADY_handshake_to_next_ARREADY_Delay : coverpoint cov_prev_handshake_ARREADY_Delay {
      bins last_arvalid_arready_handshake_to_next_arready_delay_min = {1};
      bins last_arvalid_arready_handshake_to_next_arready_delay_mid = {[2:( 16/2)]};
      bins last_arvalid_arready_handshake_to_next_arready_delay_max = {[( 16/2)+1:$]};
    }
    last_ARREADY_to_next_ARVALID_ARREADY_handshake_Delay : coverpoint cov_prev_ARREADY_to_handshake_Delay {
      bins last_arready_to_next_arvalid_arready_handshake_delay_min = {1};
      bins last_arready_to_next_arvalid_arready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_arready_to_next_arvalid_arready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay : coverpoint cov_last_RVALID_RREADY_handshake_to_next_RVALID_RREADY_handshake_Delay {
      bins last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_min = {1};
      bins last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_rvalid_rready_handshake_to_next_rvalid_rready_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    last_RVALID_RREADY_handshake_to_next_RVALID_Delay : coverpoint cov_last_RVALID_RREADY_handshake_to_next_RVALID_Delay {
      bins last_rvalid_rready_handshake_to_next_rvalid_delay_min = {1};
      bins last_rvalid_rready_handshake_to_next_rvalid_delay_mid = {[2:( 16/2)]};
      bins last_rvalid_rready_handshake_to_next_rvalid_delay_max = {[( 16/2)+1:$]};
    }
    last_RVALID_RREADY_handshake_to_next_RREADY_Delay : coverpoint cov_last_RVALID_RREADY_handshake_to_next_RREADY_Delay {
      bins last_rvalid_rready_handshake_to_next_rready_delay_min = {1};
      bins last_rvalid_rready_handshake_to_next_rready_delay_mid = {[2:( 16/2)]};
      bins last_rvalid_rready_handshake_to_next_rready_delay_max = {[( 16/2)+1:$]};
    }
    last_RREADY_to_next_RVALID_RREADY_handshake_Delay : coverpoint cov_last_RREADY_to_next_RVALID_RREADY_handshake_Delay {
      bins last_rready_to_next_rvalid_rready_handshake_delay_min = {1};
      bins last_rready_to_next_rvalid_rready_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_rready_to_next_rvalid_rready_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay : coverpoint cov_last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_Delay {
      bins last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_min = {1};
      bins last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_RVALID_RREADY_data_beat_handshake_to_next_RVALID_RREADY_first_data_beat_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_snoop

Covergroup: trans_axi_snoop

This Covergroup captures delay scenarios between valid and ready signal for snoop address and snoop data. It is constructed when trans_axi_snoop_enable is set to 1 and interface type is AXI_ACE or ACE_LITE.

Coverpoints:

ACVALID_to_ACREADY_Delay: Captures min, mid and max range of delays between signals acvalid and acready
ACVALID_to_CRVALID_Delay: Captures min, mid and max range of delays between signals acvalid and crvalid
CRVALID_to_CRREADY_Delay: Captures min, mid and max range of delays between signals crvalid and crready
ACVALID_to_prev_ACVALID_Delay: Captures min, mid and max range of delays between current and previous acvalid signals
ACVALID_before_ACREADY: Captures if ACVALID signal comes before ACREADY signal
ACREADY_before_ACVALID: Captures if ACREADY signal comes before ACVALID signal
CRVALID_before_CRREADY: Captures if CRVALID signal comes before CRREADY signal
CRREADY_before_CRVALID: Captures if CRREADY signal comes before CRVALID signal

covergroup trans_axi_snoop @ ( cov_snoop_sample_event ) ;
     option.per_instance = 1;
    ACVALID_to_ACREADY_Delay : coverpoint cov_ACVALID_to_ACREADY_Delay {
      bins acvalid_to_acready_delay_min = {0};
      bins acvalid_to_acready_delay_mid = {[1:( 16/2)]};
      bins acvalid_to_acready_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    ACVALID_to_CRVALID_Delay : coverpoint cov_ACVALID_to_CRVALID_Delay {
      bins acvalid_to_crvalid_delay_min = {[1: ((16+16)/3)]};
      bins acvalid_to_crvalid_delay_mid = {[(`MIN_UPPER_BOUND+1):( (16+16)/2)]};
      bins acvalid_to_crvalid_delay_max = {[( (16+16)/2)+1:$]};
      option.at_least = 1;
    }
    CRVALID_to_CRREADY_Delay : coverpoint cov_CRVALID_to_CRREADY_Delay {
      bins crvalid_to_crready_delay_min = {0};
      bins crvalid_to_crready_delay_mid = {[1:( 10/2)]};
      bins crvalid_to_crready_delay_max = {[( 10/2)+1:$]};
      option.at_least = 1;
    }
    ACVALID_to_prev_ACVALID_Delay : coverpoint cov_ACVALID_to_prev_ACVALID_Delay {
      bins acvalid_to_prev_acvalid_delay_min = {1};
      bins acvalid_to_prev_acvalid_delay_mid = {[2:(( 10 + 16)/2)]};
      bins acvalid_to_prev_acvalid_delay_max = {[(( 10 + 16)/2)+1:$]};
      option.at_least = 1;
    }
         ACVALID_before_ACREADY: coverpoint cov_ACVALID_before_ACREADY {
      bins acvalid_before_acready = {1};
      option.at_least = 3;
    }
    ACREADY_before_ACVALID: coverpoint cov_ACREADY_before_ACVALID {
      bins acready_before_acvalid = {1};
      option.at_least = 3;
    }
    CRVALID_before_CRREADY: coverpoint cov_CRVALID_before_CRREADY {
      bins crvalid_before_crready = {1};
      option.at_least = 3;
    }
    CRREADY_before_CRVALID: coverpoint cov_CRREADY_before_CRVALID {
      bins crready_before_crvalid = {1};
      option.at_least = 3;
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_snoop_data_phase

Covergroup: trans_axi_snoop_data_phase

This Covergroup captures valid to ready delay scenario for snoop channel. It is constructed when trans_axi_snoop_enable is set to 1.

Coverpoints:

CDVALID_to_prev_CDVALID_Delay
CDVALID_to_CDREADY_Delay
CDVALID_before_CDREADY: Captures if CDVALID signal comes before CDREADY signal
CDREADY_before_CDVALID: Captures if CDREADY signal comes before CDVALID signal

covergroup trans_axi_snoop_data_phase @ ( cov_snoop_per_beat_sample_event ) ;
     option.per_instance = 1;
    CDVALID_to_prev_CDVALID_Delay : coverpoint cov_CDVALID_to_prev_CDVALID_Delay {
      bins cdvalid_to_prev_cdvalid_delay_min = {1};
      bins cdvalid_to_prev_cdvalid_delay_mid = {[2:(( 16 + 10)/2)]};
      bins cdvalid_to_prev_cdvalid_delay_max = {[(( 16 + 10)/2)+1:$]};
      option.at_least = 1;
    }
    CDVALID_to_CDREADY_Delay : coverpoint cov_CDVALID_to_CDREADY_Delay {
      bins cdvalid_to_cdready_delay_min = {0};
      bins cdvalid_to_cdready_delay_mid = {[1:( 10/2)]};
      bins cdvalid_to_cdready_delay_max = {[( 10/2)+1:$]};
      option.at_least = 1;
    }
    CDVALID_before_CDREADY: coverpoint cov_CDVALID_before_CDREADY {
      bins cdvalid_before_cdready = {1};
      option.at_least = 3;
    }
    CDREADY_before_CDVALID: coverpoint cov_CDREADY_before_CDVALID {
      bins cdready_before_cdvalid = {1};
      option.at_least = 3;
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_snoop_idle_chan_with_acwakeup

Covergroup: trans_axi_snoop_idle_chan_with_acwakeup

This Covergroup captures wakeup and valid signal delay scenario for idle snoop address channel. It is constructed when acwakeup_enable is set to 1 and port_kind is AXI_SLAVE.

Coverpoints:

ACWAKEUP_toggle_Delay_idle_snoop_chan: Captures min, mid and max range of acwakeup toggle delay during idle period of snoop channel

covergroup trans_axi_snoop_idle_chan_with_acwakeup @ ( cov_snoop_sample_event_for_idle_snoop_chan ) ;
     ACWAKEUP_toggle_Delay_idle_snoop_chan : coverpoint cov_ACWAKEUP_toggle_Delay_idle_snoop_chan {
      bins acwakeup_after_acvalid_min = {cfg_acwakeup_toggle_min_delay_during_idle};
      bins acwakeup_after_acvalid_mid = {[(cfg_acwakeup_toggle_min_delay_during_idle+1):(cfg_acwakeup_toggle_max_delay_during_idle)/2]};
      bins acwakeup_after_acvalid_max = {[(cfg_acwakeup_toggle_max_delay_during_idle/2)+1:cfg_acwakeup_toggle_max_delay_during_idle]};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_snoop_idle_chan_with_awakeup

Covergroup: trans_axi_snoop_idle_chan_with_awakeup

This Covergroup captures wakeup and valid signal delay scenario . It is constructed when acwakeup_enable is set to 1 and port_kind is AXI_MASTER.

Coverpoints:

AWAKEUP_toggle_Delay_idle_snoop_chan: Captures min, mid and max range of awakeup toggle delay during idle period of snoop channel

covergroup trans_axi_snoop_idle_chan_with_awakeup @ ( cov_snoop_sample_event_for_awakeup_idle_snoop_chan ) ;
     option.per_instance = 1;
    AWAKEUP_toggle_Delay_idle_snoop_chan : coverpoint cov_AWAKEUP_toggle_Delay_idle_snoop_chan {
        bins awakeup_after_arvalid_min = {cfg_awakeup_toggle_min_delay_during_idle};
        bins awakeup_after_arvalid_mid = {[(cfg_awakeup_toggle_min_delay_during_idle+1):(cfg_awakeup_toggle_max_delay_during_idle)/2]};
        bins awakeup_after_arvalid_max = {[(cfg_awakeup_toggle_max_delay_during_idle/2)+1:cfg_awakeup_toggle_max_delay_during_idle]};
      }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_snoop_with_acwakeup

Covergroup: trans_axi_snoop_with_acwakeup

This Covergroup captures wakeup and valid signal delay scenario for snoop address channel. It is constructed when acwakeup_enable is set to 1 and port_kind is AXI_SLAVE.

Coverpoints:

ACWAKEUP_before_ACVALID_Delay: Captures min, mid and max range of delays between signals acwakeup to acvalid
ACWAKEUP_after_ACVALID_Delay: Captures min, mid and max range of delays between signals acvalid to acwakeup
ACWAKEUP_ACVALID_same_time: Captures delays of signals acwakeup and acvalid assertion same time
ACWAKEUP_to_prev_ACWAKEUP_Delay: Captures min, mid and max range of delays between signals acwakeup to previous acwakeup

covergroup trans_axi_snoop_with_acwakeup @ ( cov_snoop_sample_event ) ;
     option.per_instance = 1;
    ACWAKEUP_before_ACVALID_Delay : coverpoint cov_ACWAKEUP_before_ACVALID_Delay {
      bins acwakeup_before_acvalid_min = { 0};
      bins acwakeup_before_acvalid_mid = {[`SVT_AXI_MIN_ACWAKEUP_ASSERT_DELAY+1:( 6/2)]};
      bins acwakeup_before_acvalid_max = {[( 6/2)+1: 6]};
    }
    ACWAKEUP_after_ACVALID_Delay : coverpoint cov_ACWAKEUP_after_ACVALID_Delay {
      bins acwakeup_after_acvalid_min = { 0};
      bins acwakeup_after_acvalid_mid = {[`SVT_AXI_MIN_ACWAKEUP_ASSERT_DELAY+1:( 6/2)]};
      bins acwakeup_after_acvalid_max = {[( 6/2)+1: 6]};
    }
    ACWAKEUP_ACVALID_same_time : coverpoint cov_ACWAKEUP_ACVALID_same_time {
      bins acwakeup_acvalid_same_time = {0};
    }
     ACWAKEUP_to_prev_ACWAKEUP_Delay : coverpoint cov_ACWAKEUP_to_prev_ACWAKEUP_Delay {
      bins acwakeup_to_prev_acwakeup_delay_min = {2};
      bins acwakeup_to_prev_acwakeup_delay_mid = {[3:(( 10 + 16 + 6)/3)]};
      bins acwakeup_to_prev_acwakeup_delay_max = {[(( 10 + 16 + 6)/3)+1:$]};
     }
     endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_axi_write_handshake_delay

Covergroup: trans_axi_write_handshake_delay

This Covergroup captures handshaking between valid and ready signal for diferent delay scenarios for write address and write data channels. It is constructed and sampled when interface type is not AXI_READ_ONLY.

Coverpoints:

last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay:Captures min, mid and max range of delays between last awvalid_awready handshake to the next awvalid_awready handshake
last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awvalid
last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay: Captures min,mid and max range of delays between last awvalid_awready handshake to the next awready
last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay: Captures min,mid and max range of delays between last awready to the next awvalid_awready handshake
last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid_wready handshake
last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay: Captures min, mid and max range of delays between last wvalid_wready data beat handshake to the next wvalid_wready data beat handshake
last_WVALID_WREADY_handshake_to_next_WVALID_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wvalid
last_WVALID_WREADY_handshake_to_next_WREADY_Delay: Captures min, mid and max range of delays between last wvalid_wready handshake to the next wready
last_WREADY_to_next_WVALID_WREADY_handshake_Delay: Captures min,mid and max range of delays between last wready to the next wvalid_wready handshake
last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay:Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid_bready handshake
last_BVALID_BREADY_handshake_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bvalid
last_BVALID_BREADY_handshake_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bvalid_bready handshake to the next bready
last_BVALID_to_next_BVALID_Delay: Captures min, mid and max range of delays between last bvalid to the next bvalid
last_BREADY_to_next_BREADY_Delay: Captures min, mid and max range of delays between last bready to the next bready
last_BREADY_to_next_BVALID_BREADY_handshake_Delay: Captures min, mid and max range of delays between last bready to the next bvalid_bready handshake

covergroup trans_axi_write_handshake_delay;
     option.per_instance = 1;
    last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay : coverpoint cov_last_AWVALID_AWREADY_handshake_to_next_AWVALID_AWREADY_handshake_Delay {
      bins last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_min = {1};
      bins last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_awvalid_awready_handshake_to_next_awvalid_awready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    last_AWVALID_AWREADY_handshake_to_next_AWVALID_Delay : coverpoint cov_prev_handshake_AWVALID_Delay {
      bins last_awvalid_awready_handshake_to_next_awvalid_delay_min = {1};
      bins last_awvalid_awready_handshake_to_next_awvalid_delay_mid = {[2:( 16/2)]};
      bins last_awvalid_awready_handshake_to_next_awvalid_delay_max = {[( 16/2)+1:$]};
    }
    last_AWVALID_AWREADY_handshake_to_next_AWREADY_Delay : coverpoint cov_prev_handshake_AWREADY_Delay {
      bins last_awvalid_awready_handshake_to_next_awready_delay_min = {1};
      bins last_awvalid_awready_handshake_to_next_awready_delay_mid = {[2:( 16/2)]};
      bins last_awvalid_awready_handshake_to_next_awready_delay_max = {[( 16/2)+1:$]};
    }
    last_AWREADY_to_next_AWVALID_AWREADY_handshake_Delay : coverpoint cov_prev_AWREADY_to_handshake_Delay {
      bins last_awready_to_next_awvalid_awready_handshake_delay_min = {1};
      bins last_awready_to_next_awvalid_awready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_awready_to_next_awvalid_awready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay : coverpoint cov_last_WVALID_WREADY_handshake_to_next_WVALID_WREADY_handshake_Delay {
      bins last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_min = {1};
      bins last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_wvalid_wready_handshake_to_next_wvalid_wready_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay : coverpoint cov_last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_Delay {
      bins last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_min = {1};
      bins last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_WVALID_WREADY_data_beat_handshake_to_next_WVALID_WREADY_first_data_beat_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    last_WVALID_WREADY_handshake_to_next_WVALID_Delay : coverpoint cov_last_WVALID_WREADY_handshake_to_next_WVALID_Delay {
      bins last_wvalid_wready_handshake_to_next_wvalid_delay_min = {1};
      bins last_wvalid_wready_handshake_to_next_wvalid_delay_mid = {[2:( 16/2)]};
      bins last_wvalid_wready_handshake_to_next_wvalid_delay_max = {[( 16/2)+1:$]};
    }
    last_WVALID_WREADY_handshake_to_next_WREADY_Delay : coverpoint cov_last_WVALID_WREADY_handshake_to_next_WREADY_Delay {
      bins last_wvalid_wready_handshake_to_next_wready_delay_min = {1};
      bins last_wvalid_wready_handshake_to_next_wready_delay_mid = {[2:( 16/2)]};
      bins last_wvalid_wready_handshake_to_next_wready_delay_max = {[( 16/2)+1:$]};
    }
    last_WREADY_to_next_WVALID_WREADY_handshake_Delay : coverpoint cov_last_WREADY_to_next_WVALID_WREADY_handshake_Delay {
      bins last_wready_to_next_wvalid_wready_handshake_delay_min = {1};
      bins last_wready_to_next_wvalid_wready_handshake_delay_mid = {[2:(( 16 + 16)/2)]};
      bins last_wready_to_next_wvalid_wready_handshake_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay : coverpoint cov_last_BVALID_BREADY_handshake_to_next_BVALID_BREADY_handshake_Delay {
      bins last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_min = {1};
      bins last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_bvalid_bready_handshake_to_next_bvalid_bready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    last_BVALID_BREADY_handshake_to_next_BVALID_Delay : coverpoint cov_last_BVALID_BREADY_handshake_to_next_BVALID_Delay {
      bins last_bvalid_bready_handshake_to_next_bvalid_delay_min = {1};
      bins last_bvalid_bready_handshake_to_next_bvalid_delay_mid = {[2:( 16/2)]};
      bins last_bvalid_bready_handshake_to_next_bvalid_delay_max = {[( 16/2)+1:$]};
    }
    last_BVALID_BREADY_handshake_to_next_BREADY_Delay : coverpoint cov_last_BVALID_BREADY_handshake_to_next_BREADY_Delay {
      bins last_bvalid_bready_handshake_to_next_bready_delay_min = {1};
      bins last_bvalid_bready_handshake_to_next_bready_delay_mid = {[2:( 16/2)]};
      bins last_bvalid_bready_handshake_to_next_bready_delay_max = {[( 16/2)+1:$]};
    }
    last_BVALID_to_next_BVALID_Delay : coverpoint cov_BVALID_to_next_BVALID_Delay {
      bins last_BVALID_to_next_BVALID_delay_min = {1};
      bins last_BVALID_to_next_BVALID_delay_mid = {[2:( 16/2)]};
      bins last_BVALID_to_next_BVALID_delay_max = {[( 16/2)+1:$]};
    }
    last_BREADY_to_next_BREADY_Delay : coverpoint cov_last_BREADY_to_next_BREADY_Delay {
      bins last_BREADY_to_next_BREADY_delay_min = {1};
      bins last_BREADY_to_next_BREADY_delay_mid = {[2:( 16/2)]};
      bins last_BREADY_to_next_BREADY_delay_max = {[( 16/2)+1:$]};
    }
    last_BREADY_to_next_BVALID_BREADY_handshake_Delay : coverpoint cov_last_BREADY_to_next_BVALID_BREADY_handshake_Delay {
      bins last_bready_to_next_bvalid_bready_handshake_delay_min = {1};
      bins last_bready_to_next_bvalid_bready_handshake_delay_mid = {[2:( 16/2)]};
      bins last_bready_to_next_bvalid_bready_handshake_delay_max = {[( 16/2)+1:$]};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acdvmmessage_acdvmresp

Covergroup: trans_cross_ace_acdvmmessage_acdvmresp

This covergroup captures snoop dvm message and response type. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acdvmmessage_acdvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

acdvm_message_type : Captures DVM message on acaddr[14:12]
acdvm_resp : Capture DVM response on crresp, accept = 5'b00000 and reject = 5'b00010

Cross coverpoints:

acdvmmessage_acdvmresp : Crosses coverpoints acdvm_message_type and acdvm_resp

covergroup trans_cross_ace_acdvmmessage_acdvmresp @ ( cov_snoop_sample_event ) ;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag) {
    bins message_tlb_invalidate = {3'b000};
    bins message_branch_predictor_invalidate = {3'b001};
    bins message_physical_instruction_cache_invalidate = {3'b010};
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    bins message_synchronization = {3'b100};
    bins message_hint = {3'b110};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_resp : coverpoint cov_crresp iff(cov_acdvm_message_flag){
    bins message_accept = {5'b00000};
    bins message_reject = {5'b00010};
    option.weight = 0;
  }
     acdvmmessage_acdvmresp : cross acdvm_message_type ,acdvm_resp {
        ignore_bins Ignore_dvm_hint_msg_resp = (binsof (acdvm_message_type) intersect {3'b110}) &&
                                               (binsof (acdvm_resp) intersect {5'b00010});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acaddr_dvm_set

Covergroup: trans_cross_ace_acsnoop_acaddr_dvm_set

This Covergroup captures snoop xact type and address. It is constructed when dvm_enable is set to 1. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acaddr_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_addr : Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses cover points snoop_xact_type and snoop_addr

covergroup trans_cross_ace_acsnoop_acaddr_dvm_set @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_addr : coverpoint cov_snoop_item.snoop_addr iff(cov_snoop_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0};
       bins addr_range_mid = {[1:(64'd2**(64)-2)]};
     bins addr_range_max = {((64'd2**(64))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(64))-1)};
    ignore_bins Ignore_addr_range_min = {0};
  }
     acsnoop_acaddr : cross snoop_xact_type, snoop_addr {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acaddr_dvm_set_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_acaddr_dvm_set_one_ace_acelite

This covergroup captures snoop xact type and address. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acaddr_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_addr : Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses coverpoints snoop_xact_type and snoop_addr

covergroup trans_cross_ace_acsnoop_acaddr_dvm_set_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_addr : coverpoint cov_snoop_item.snoop_addr iff(cov_snoop_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0};
       bins addr_range_mid = {[1:(64'd2**(64)-2)]};
     bins addr_range_max = {((64'd2**(64))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(64))-1)};
    ignore_bins Ignore_addr_range_min = {0};
  }
     acsnoop_acaddr : cross snoop_xact_type, snoop_addr {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acaddr_dvm_unset

Covergroup: trans_cross_ace_acsnoop_acaddr_dvm_unset

This covergroup captures snoop xact type and address. This covergroup will be created when there is more than 2 ACE-masters in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acaddr_enable = 1 svt_axi_port_configuration :: dvm_enable = 0.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_addr : Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses coverpoints snoop_xact_type and snoop_addr

covergroup trans_cross_ace_acsnoop_acaddr_dvm_unset @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_addr : coverpoint cov_snoop_item.snoop_addr iff(cov_snoop_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0};
       bins addr_range_mid = {[1:(64'd2**(64)-2)]};
     bins addr_range_max = {((64'd2**(64))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(64))-1)};
    ignore_bins Ignore_addr_range_min = {0};
  }
     acsnoop_acaddr : cross snoop_xact_type, snoop_addr {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acaddr_dvm_unset_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_acaddr_dvm_unset_one_ace_acelite

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_addr : Captures Snoop address

Cross coverpoints:

acsnoop_acaddr : Crosses coverpoints snoop_xact_type and snoop_addr

covergroup trans_cross_ace_acsnoop_acaddr_dvm_unset_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_addr : coverpoint cov_snoop_item.snoop_addr iff(cov_snoop_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0};
       bins addr_range_mid = {[1:(64'd2**(64)-2)]};
     bins addr_range_max = {((64'd2**(64))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(64))-1)};
    ignore_bins Ignore_addr_range_min = {0};
  }
     acsnoop_acaddr : cross snoop_xact_type, snoop_addr {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acprot_dvm_set

Covergroup: trans_cross_ace_acsnoop_acprot_dvm_set

This covergroup captures snoop xact type and protection signal. This covergroup will be created when there is only one ACE-master. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acprot_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_prot : Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses coverpoints snoop_xact_type and snoop_prot

covergroup trans_cross_ace_acsnoop_acprot_dvm_set @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_prot : coverpoint cov_snoop_item.snoop_prot iff(cov_snoop_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_acprot : cross snoop_xact_type, snoop_prot {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acprot_dvm_set_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_acprot_dvm_set_one_ace_acelite

This covergroup captures snoop xact type and protection signal. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acprot_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_prot : Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses coverpoints snoop_xact_type and snoop_prot

covergroup trans_cross_ace_acsnoop_acprot_dvm_set_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_prot : coverpoint cov_snoop_item.snoop_prot iff(cov_snoop_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_acprot : cross snoop_xact_type, snoop_prot {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acprot_dvm_unset

Covergroup : trans_cross_ace_acsnoop_acprot_dvm_unset

This covergroup captures snoop xact type and protection signal. This covergroup will be created when there is more than 2 ACE-masters in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_acprot_enable = 1 svt_axi_port_configuration :: dvm_enable = 0.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_prot : Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses coverpoints snoop_xact_type and snoop_prot

covergroup trans_cross_ace_acsnoop_acprot_dvm_unset @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_prot : coverpoint cov_snoop_item.snoop_prot iff(cov_snoop_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_acprot : cross snoop_xact_type, snoop_prot {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_acprot_dvm_unset_one_ace_acelite

Covergroup : trans_cross_ace_acsnoop_acprot_dvm_unset_one_ace_acelite

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_prot : Captures Snoop protection type

Cross coverpoints:

acsnoop_acprot : Crosses coverpoints snoop_xact_type and snoop_prot

covergroup trans_cross_ace_acsnoop_acprot_dvm_unset_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_prot : coverpoint cov_snoop_item.snoop_prot iff(cov_snoop_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_acprot : cross snoop_xact_type, snoop_prot {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_crresp_dvm_set

Covergroup: trans_cross_ace_acsnoop_crresp_dvm_set

This covergroup captures snoop xact_type, rresp_type(unique and notunique). This covergroup will be created when there are more than 2 ACE-masters in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_crresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_crresp : Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses coverpoints snoop_xact_type and snoop_crresp

covergroup trans_cross_ace_acsnoop_crresp_dvm_set @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp : coverpoint cov_crresp[3:0] iff(cov_snoop_resp_flag){
    bins cresp_x0000 = {4'b0000};
    bins cresp_x1000 = {4'b1000};
    bins cresp_x0001 = {4'b0001};
    bins cresp_x1001 = {4'b1001};
    bins cresp_x0101 = {4'b0101};
    bins cresp_x1101 = {4'b1101};
    wildcard ignore_bins ig_invalid_cresp1 = {5'b??1?0};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp_wu : coverpoint cov_crresp[4] iff(cov_snoop_resp_flag){
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_crresp : cross snoop_xact_type, snoop_crresp {
      ignore_bins Ig_invalid_cresp2 = (binsof(snoop_crresp) intersect {4'b1000, 4'b1001, 4'b1010, 4'b1011,
                                                                      4'b1100, 4'b1101, 4'b1110, 4'b1111}) &&
                                     (binsof(snoop_xact_type) intersect {svt_axi_snoop_transaction::READUNIQUE,
                                                              svt_axi_snoop_transaction::CLEANINVALID, svt_axi_snoop_transaction::MAKEINVALID});
    option.weight = 1;
     }
     acsnoop_crresp_wasunique : cross snoop_xact_type, snoop_crresp_wu {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_crresp_dvm_set_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_crresp_dvm_set_one_ace_acelite

This covergroup captures snoop xact_type, rresp_type(unique and notunique). This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_crresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_crresp : Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses coverpoints snoop_xact_type and snoop_crresp

covergroup trans_cross_ace_acsnoop_crresp_dvm_set_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp : coverpoint cov_crresp[3:0] iff(cov_snoop_resp_flag){
    bins cresp_x0000 = {4'b0000};
    bins cresp_x1000 = {4'b1000};
    bins cresp_x0001 = {4'b0001};
    bins cresp_x1001 = {4'b1001};
    bins cresp_x0101 = {4'b0101};
    bins cresp_x1101 = {4'b1101};
    wildcard ignore_bins ig_invalid_cresp1 = {5'b??1?0};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp_wu : coverpoint cov_crresp[4] iff(cov_snoop_resp_flag){
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_crresp : cross snoop_xact_type, snoop_crresp {
      ignore_bins Ig_invalid_cresp2 = (binsof(snoop_crresp) intersect {4'b1000, 4'b1001, 4'b1010, 4'b1011,
                                                                      4'b1100, 4'b1101, 4'b1110, 4'b1111}) &&
                                     (binsof(snoop_xact_type) intersect {svt_axi_snoop_transaction::READUNIQUE,
                                                              svt_axi_snoop_transaction::CLEANINVALID, svt_axi_snoop_transaction::MAKEINVALID});
    option.weight = 1;
     }
     acsnoop_crresp_wasunique : cross snoop_xact_type, snoop_crresp_wu {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_crresp_dvm_unset

Covergroup: trans_cross_ace_acsnoop_crresp_dvm_unset

This covergroup captures snoop xact_type, rresp_type(unique and notunique). This covergroup will be created when there is are more than 2 ACE masters in the system. It is constructed when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: trans_cross_ace_acsnoop_crresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 0.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_crresp : Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses coverpoints snoop_xact_type and snoop_crresp

covergroup trans_cross_ace_acsnoop_crresp_dvm_unset @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp : coverpoint cov_crresp[3:0] iff(cov_snoop_resp_flag){
    bins cresp_x0000 = {4'b0000};
    bins cresp_x1000 = {4'b1000};
    bins cresp_x0001 = {4'b0001};
    bins cresp_x1001 = {4'b1001};
    bins cresp_x0101 = {4'b0101};
    bins cresp_x1101 = {4'b1101};
    wildcard ignore_bins ig_invalid_cresp1 = {5'b??1?0};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp_wu : coverpoint cov_crresp[4] iff(cov_snoop_resp_flag){
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_crresp : cross snoop_xact_type, snoop_crresp {
      ignore_bins Ig_invalid_cresp2 = (binsof(snoop_crresp) intersect {4'b1000, 4'b1001, 4'b1010, 4'b1011,
                                                                      4'b1100, 4'b1101, 4'b1110, 4'b1111}) &&
                                     (binsof(snoop_xact_type) intersect {svt_axi_snoop_transaction::READUNIQUE,
                                                              svt_axi_snoop_transaction::CLEANINVALID, svt_axi_snoop_transaction::MAKEINVALID});
    option.weight = 1;
      }
     acsnoop_crresp_wasunique : cross snoop_xact_type, snoop_crresp_wu {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_crresp_dvm_unset_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_crresp_dvm_unset_one_ace_acelite

Coverpoints:

snoop_xact_type : Captures Snoop transaction
snoop_crresp : Captures Snoop response type

Cross coverpoints:

acsnoop_crresp : Crosses coverpoints snoop_xact_type and snoop_crresp

covergroup trans_cross_ace_acsnoop_crresp_dvm_unset_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp : coverpoint cov_crresp[3:0] iff(cov_snoop_resp_flag){
    bins cresp_x0000 = {4'b0000};
    bins cresp_x1000 = {4'b1000};
    bins cresp_x0001 = {4'b0001};
    bins cresp_x1001 = {4'b1001};
    bins cresp_x0101 = {4'b0101};
    bins cresp_x1101 = {4'b1101};
    wildcard ignore_bins ig_invalid_cresp1 = {5'b??1?0};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_crresp_wu : coverpoint cov_crresp[4] iff(cov_snoop_resp_flag){
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     acsnoop_crresp : cross snoop_xact_type, snoop_crresp {
      ignore_bins Ig_invalid_cresp2 = (binsof(snoop_crresp) intersect {4'b1000, 4'b1001, 4'b1010, 4'b1011,
                                                                      4'b1100, 4'b1101, 4'b1110, 4'b1111}) &&
                                     (binsof(snoop_xact_type) intersect {svt_axi_snoop_transaction::READUNIQUE,
                                                              svt_axi_snoop_transaction::CLEANINVALID, svt_axi_snoop_transaction::MAKEINVALID});
    option.weight = 1;
      }
     acsnoop_crresp_wasunique : cross snoop_xact_type, snoop_crresp_wu {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate

This covergroup captures snoop_xact_type, snoop initial and final cache line state for snoop based transaction. This covergroup will be created when there are more than 2 ACE-masters in the system. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: is_active = 1 svt_axi_port_configuration :: is_active = 0 with svt_axi_system_configuration :: passive_cache_monitor_enable = 1 svt_axi_port_configuration :: trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints snoop_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_snoop_item.snoop_initial_cache_line_state iff (cov_snoop_initial_cache_line_state_flag) {
      bins initial_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins initial_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins initial_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins initial_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins initial_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     final_cache_line_state : coverpoint cov_snoop_item.snoop_final_cache_line_state iff (cov_snoop_final_cache_line_state_flag) {
      bins final_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins final_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins final_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins final_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins final_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     acsnoop_cacheinitialstate_cachefinalstate : cross snoop_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_rc_rnsd_rs_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                    svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                   svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                   svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                           ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                   svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                   svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                             (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READCLEAN,
                                                     svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_snoop_transaction::READSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READCLEAN,
                                                     svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_snoop_transaction::READSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ru_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READUNIQUE}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
       ignore_bins Ignore_readonce_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                    svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ci_mi_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::CLEANINVALID,
                                                    svt_axi_snoop_transaction::MAKEINVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
      ignore_bins Ignore_cleanshared_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDCLEAN,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_dvm_xact_type = binsof(snoop_xact_type) intersect
                                            { svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate_one_ace_acelite

This covergroup captures snoop_xact_type, snoop initial and final cache line state for snoop based transaction. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: is_active = 1 svt_axi_port_configuration :: is_active = 0 with svt_axi_system_configuration :: passive_cache_monitor_enable = 1 svt_axi_port_configuration :: trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints snoop_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_acsnoop_dvm_set_cacheinitialstate_cachefinalstate_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    bins snoop_dvmcomplete_xact = {svt_axi_snoop_transaction::DVMCOMPLETE};
    bins snoop_dvmmessage_xact = {svt_axi_snoop_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_snoop_item.snoop_initial_cache_line_state iff (cov_snoop_initial_cache_line_state_flag) {
      bins initial_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins initial_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins initial_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins initial_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins initial_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     final_cache_line_state : coverpoint cov_snoop_item.snoop_final_cache_line_state iff (cov_snoop_final_cache_line_state_flag) {
      bins final_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins final_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins final_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins final_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins final_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     acsnoop_cacheinitialstate_cachefinalstate : cross snoop_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_readonce_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                    svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ci_mi_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::CLEANINVALID,
                                                    svt_axi_snoop_transaction::MAKEINVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
      ignore_bins Ignore_cleanshared_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDCLEAN,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_dvm_xact_type = binsof(snoop_xact_type) intersect
                                            { svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate

This covergroup captures snoop_xact_type, snoop initial and final cache line state for snoop based transaction. This covergroup will be created when there are more than two ACE-masters in the system. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: is_active = 1 svt_axi_port_configuration :: is_active = 0 with svt_axi_system_configuration :: passive_cache_monitor_enable = 1 svt_axi_port_configuration :: trans_cross_ace_acsnoop_cacheinitialstate_cachefinalstate_enable = 1 svt_axi_port_configuration :: dvm_enable = 0.

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints snoop_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_snoop_item.snoop_initial_cache_line_state iff (cov_snoop_initial_cache_line_state_flag) {
      bins initial_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins initial_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins initial_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins initial_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins initial_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     final_cache_line_state : coverpoint cov_snoop_item.snoop_final_cache_line_state iff (cov_snoop_final_cache_line_state_flag) {
      bins final_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins final_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins final_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins final_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins final_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     acsnoop_cacheinitialstate_cachefinalstate : cross snoop_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_rc_rnsd_rs_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                    svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                   svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                   svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                           ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READCLEAN,
                                                   svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                   svt_axi_snoop_transaction::READSHARED}) &&
                                             (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                             (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READCLEAN,
                                                     svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_snoop_transaction::READSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READCLEAN,
                                                     svt_axi_snoop_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_snoop_transaction::READSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ru_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::READUNIQUE}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
       ignore_bins Ignore_readonce_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                    svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ci_mi_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::CLEANINVALID,
                                                    svt_axi_snoop_transaction::MAKEINVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
      ignore_bins Ignore_cleanshared_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDCLEAN,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN}));
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate_one_ace_acelite

Covergroup: trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate_one_ace_acelite

Coverpoints:

snoop_xact_type : Captures Snoop transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

acsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints snoop_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_acsnoop_dvm_unset_cacheinitialstate_cachefinalstate_one_ace_acelite @ ( cov_snoop_sample_event ) ;
      snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_snoop_item.snoop_initial_cache_line_state iff (cov_snoop_initial_cache_line_state_flag) {
      bins initial_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins initial_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins initial_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins initial_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins initial_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     final_cache_line_state : coverpoint cov_snoop_item.snoop_final_cache_line_state iff (cov_snoop_final_cache_line_state_flag) {
      bins final_state_invalid = {svt_axi_snoop_transaction::INVALID};
      bins final_state_uniqueclean = {svt_axi_snoop_transaction::UNIQUECLEAN};
      bins final_state_uniquedirty = {svt_axi_snoop_transaction::UNIQUEDIRTY};
      bins final_state_sharedclean = {svt_axi_snoop_transaction::SHAREDCLEAN};
      bins final_state_shareddirty = {svt_axi_snoop_transaction::SHAREDDIRTY};
      option.weight = 0 ;
      type_option.weight = 0 ;
    }
     acsnoop_cacheinitialstate_cachefinalstate : cross snoop_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_readonce_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                    svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                            ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,
                                                    svt_axi_snoop_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_ci_mi_states = ((binsof(snoop_xact_type) intersect
                                                   {svt_axi_snoop_transaction::CLEANINVALID,
                                                    svt_axi_snoop_transaction::MAKEINVALID}) &&
                                             (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
      ignore_bins Ignore_cleanshared_states = ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(snoop_xact_type) intersect
                                                    {svt_axi_snoop_transaction::CLEANSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,
                                                     svt_axi_snoop_transaction::SHAREDCLEAN,
                                                     svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,
                                                    svt_axi_snoop_transaction::SHAREDCLEAN}));
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardomain_arbarrier_memory_sync

Covergroup: trans_cross_ace_ardomain_arbarrier_memory_sync

This Covergroup captures barrier_type and domain_type for read transaction. It is constructed and sampled when trans_cross_ace_ardomain_arbarrier_memory_sync_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures read barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses cover points read transaction of certain barrier_type MEMORY_BARRIER & SYNC_BARRIER with ardomain As barrier types are memory & sync therefore, ignoring bins intersect with NORMAL_ACCESS_RESPECT_BARRIER & NORMAL_ACCESS_IGNORE_BARRIER and ignoring all other non-readbarrier bins.

covergroup trans_cross_ace_ardomain_arbarrier_memory_sync;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_READ_XACT_TYPE(`SVT_AXI_COV_WEIGHT_VAL_0)
    coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
      option.weight = 0;
    }
    // Only MEMORY_BARRIER and SYNC_BARRIER are being covered, so we need to use only the BARRIER_SET macro
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_BARRIER_TYPE
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardomain_arbarrier_memory_sync : cross coherent_read_xact_type, barrier_type, domain_type {
       ignore_bins ignore_normal = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins ignore_non_read_barrier = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_set

Covergroup: trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_set

This covergroup captures barrier_type and domain_type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_ardomain_arbarrier_respect_ignore_enable = 1 svt_axi_port_configuration :: barrier_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures non read barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses coverpoints read transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with ardomain
As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are READBARRIER with Memory & Sync

covergroup trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
    ardomain_arbarrier_respect_ignore : cross coherent_read_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER, svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_read_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE, svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::DVMMESSAGE,
                                                                                               svt_axi_transaction::DVMCOMPLETE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE, svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                                                               svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_unset

Covergroup: trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures non read barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses coverpoints read transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with ardomain
As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are READBARRIER with Memory & Sync

covergroup trans_cross_ace_ardomain_arbarrier_respect_ignore_ace_lite_dvm_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
    ardomain_arbarrier_respect_ignore : cross coherent_read_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER, svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_read_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE, svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE, svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                                                               svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_set

Covergroup: trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_set

This covergroup captures barrier_type and domain_type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_ardomain_arbarrier_respect_ignore_enable = 1 svt_axi_port_configuration :: barrier_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures non read barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses cove points read transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with ardomain
As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are READBARRIER with Memory & Sync

covergroup trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
    ardomain_arbarrier_respect_ignore : cross coherent_read_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER, svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_read_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE, svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                                                               svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                                                               svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                                                               svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                                                               svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE, svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                                                               svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_unset

Covergroup: trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures non read barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

arbarrier_ardomain : Crosses coverpoints read transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with ardomain
As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are READBARRIER with Memory & Sync

covergroup trans_cross_ace_ardomain_arbarrier_respect_ignore_dvm_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
    ardomain_arbarrier_respect_ignore : cross coherent_read_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER, svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_read_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE, svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                                                               svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                                                               svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                                                               svt_axi_transaction::MAKEUNIQUE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE, svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                                                               svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_ardvmmessage_ardvmresp

Covergroup: trans_cross_ace_ardvmmessage_ardvmresp

This Covergroup captures coherant read xact_type and response type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_ardvmmessage_ardvmresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1

Coverpoints:

ardvm_message_type : Captures DVM message on araddr[14:12]
ardvm_resp : Capture DVM response on rresp [4:0], accept = 4'b0000 and reject = 4'b0010

Cross coverpoints:

ardvmmessage_ardvmresp : Crosses coverpoints ardvm_message_type and ardvm_resp

covergroup trans_cross_ace_ardvmmessage_ardvmresp;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    bins message_branch_predictor_invalidate = {3'b001};
    bins message_physical_instruction_cache_invalidate = {3'b010};
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    bins message_synchronization = {3'b100};
    bins message_hint = {3'b110};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_resp : coverpoint cov_dvm_rresp iff(cov_ardvm_message_flag){
    bins message_accept = {4'b0000};
    bins message_reject = {4'b0010};
    option.weight = 0;
    type_option.weight = 0;
  }
    ardvmmessage_ardvmresp : cross ardvm_message_type, ardvm_resp {
      ignore_bins Ignore_dvm_hint_msg_resp = (binsof(ardvm_message_type) intersect {3'b110, 3'b100}) &&
                                             (binsof(ardvm_resp) intersect {4'b0010});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arprot_arbarrier_memory_sync

Covergroup: trans_cross_ace_arprot_arbarrier_memory_sync

It is constructed and sampled when trans_cross_ace_arprot_arbarrier_memory_sync_enable is asserted.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
barrier_type : Captures read barrier
prot_type : Captures transaction protection type

Cross coverpoints:

arprot_arbarrier_memory_sync: Crosses cover points read transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with arprot

The following bins are ignored:

bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER
bins that intersect transaction types other than READBARRIER
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_ace_arprot_arbarrier_memory_sync;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_READ_XACT_TYPE(`SVT_AXI_COV_WEIGHT_VAL_0)
    coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    // Only MEMORY_BARRIER and SYNC_BARRIER are being covered, so we need to use only the BARRIER_SET macro
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_BARRIER_TYPE
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
     arprot_arbarrier_memory_sync : cross coherent_read_xact_type, barrier_type, prot_type {
       ignore_bins ignore_normal = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins ignore_non_read_barrier = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_araddr_ace_lite_barrier_set

This Covergroup captures coherant read xact_type and address ranges for read transaction. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_araddr_enable set to 1, & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses cover points coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_ace_lite_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                         svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_araddr_ace_lite_barrier_set

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses cover points coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_ace_lite_barrier_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                         svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_def

Covergroup: trans_cross_ace_arsnoop_araddr_def

This Covergroup captures coherant read xact_type and address ranges for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_araddr_enable set to 1, dvm_enable & barrier_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses cover points coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_def;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                         svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_araddr_dvm_set_barrier_set

This covergroup captures coherant read xact_type and address ranges for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_araddr_enable = 1 svt_axi_port_configuration :: barrier_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses coverpoints coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_dvm_set_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                          svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_araddr_dvm_set_barrier_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses coverpoints coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_dvm_set_barrier_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                          svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_araddr_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_araddr_dvm_unset_barrier_set

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
addr : Captures transaction read address

Cross coverpoints:

arsnoop_araddr : Crosses coverpoints coherent_read_xact_type and addr

covergroup trans_cross_ace_arsnoop_araddr_dvm_unset_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    arsnoop_araddr : cross coherent_read_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                          svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arbar_dvm_set

Covergroup: trans_cross_ace_arsnoop_arbar_dvm_set

This covergroup captures coherant read xact_type and barrier_type for read transaction. It is constructed and sampled when when svt_axi_port_configuration :: axi_interface_type is ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arbar_enable = 1 svt_axi_port_configuration :: barrier_enable = 1 svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures read barrier

Cross coverpoints:

arsnoop_arbar : Crosses coverpoints coherent_read_xact_type and barrier_type

covergroup trans_cross_ace_arsnoop_arbar_dvm_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arbar : cross coherent_read_xact_type, barrier_type {
      ignore_bins Ignore_normal = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                    svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
      ignore_bins Ignore_barrier = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                    svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arbar_dvm_unset

Covergroup: trans_cross_ace_arsnoop_arbar_dvm_unset

This covergroup captures coherant read xact_type and barrier_type for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arbar_enable = 1 svt_axi_port_configuration :: barrier_enable = 1 svt_axi_port_configuration :: dvm_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
barrier_type : Captures read barrier

Cross coverpoints:

arsnoop_arbar : Crosses coverpoints coherent_read_xact_type and barrier_type

covergroup trans_cross_ace_arsnoop_arbar_dvm_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arbar : cross coherent_read_xact_type, barrier_type {
      ignore_bins Ignore_normal = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                    svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
      ignore_bins Ignore_barrier = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                    svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_arburst_ace_lite_barrier_set

This Covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when interface_type is ACE_LITE ,trans_cross_ace_arsnoop_arburst_enable is set to 1 and barier_enable & dvm_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_type: Captures transaction burst type

Cross coverpoints:

arsnoop_arburst : Crosses cover points coherent_read_xact_type and burst_type

covergroup trans_cross_ace_arsnoop_arburst_ace_lite_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
       ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                            svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arburst_ace_lite_barrier_set

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_type: Captures transaction burst type

Cross coverpoints:

arsnoop_arburst : Crosses cover points coherent_read_xact_type and burst_type

covergroup trans_cross_ace_arsnoop_arburst_ace_lite_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
       ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                            svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_def

Covergroup: trans_cross_ace_arsnoop_arburst_def

This Covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when interface_type is not AXI_WRITE_ONLY ,trans_cross_ace_arsnoop_arburst_enable is set to 1 and barier_enable & dvm_enable is set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_type: Captures transaction burst type

Cross coverpoints:

arsnoop_arburst : Crosses cover points coherent_read_xact_type and burst_type

covergroup trans_cross_ace_arsnoop_arburst_def(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
       ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                            svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_arburst_dvm_set_barrier_set

This covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arburst_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_type : Captures transaction burst type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arburst : Crosses coverpoints coherent_read_xact_type and burst_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arburst_dvm_set_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id {
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                             (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                             (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                         svt_axi_transaction::DVMMESSAGE,
                                                                                         svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arburst_dvm_set_barrier_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_type : Captures transaction burst type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arburst : Crosses coverpoints coherent_read_xact_type and burst_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arburst_dvm_set_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id {
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                             (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                             (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                         svt_axi_transaction::DVMMESSAGE,
                                                                                         svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arburst_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_arburst_dvm_unset_barrier_set

This covergroup captures coherant read xact_type,burst_type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arburst_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_type : Captures transaction burst type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arburst : Crosses coverpoints coherent_read_xact_type and burst_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arburst_dvm_unset_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arburst : cross coherent_read_xact_type, burst_type , slave_port_id {
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                             (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP});
       ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                             (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                         svt_axi_transaction::DVMMESSAGE,
                                                                                         svt_axi_transaction::DVMCOMPLETE});
      // DVM, BARRIER :: alen == 0x00
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                                                        svt_axi_transaction::DVMMESSAGE,
                                                                                        svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_arcache_ace_lite_barrier_set

This Covergroup captures coherant read xact_type,cache signal and slave_port_id for read transaction. It is constructed and sampled when interface_type is ACE_LITE ,trans_cross_ace_arsnoop_arcache_enable set to 1 and barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
cache_type : Captures transaction cache type

Cross coverpoints:

arsnoop_arcache : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_arcache_ace_lite_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arcache_ace_lite_barrier_unset

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
cache_type : Captures transaction cache type

Cross coverpoints:

arsnoop_arcache : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_arcache_ace_lite_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_def

Covergroup: trans_cross_ace_arsnoop_arcache_def

This covergroup captures coherant read xact_type, cache signal and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_arcache_enable set to 1, dvm_enable and barrier_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
cache_type : Captures transaction cache type

Cross coverpoints:

arsnoop_arcache : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_arcache_def(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_arcache_dvm_set_barrier_set

This covergroup captures coherant read xact_type,cache signal and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
cache_type : Captures transaction cache type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arcache : Crosses coverpoints coherent_read_xact_type and cache_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arcache_dvm_set_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type, slave_port_id {
      ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::DVMMESSAGE,
                                                                                             svt_axi_transaction::DVMCOMPLETE}) &&
                                                 (!binsof(cache_type) intersect {4'b0010});
      ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                 (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                 (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arcache_dvm_set_barrier_unset

This covergroup captures coherant read xact_type, cache signal and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
cache_type : Captures transaction cache type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arcache : Crosses coverpoints coherent_read_xact_type and cache_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arcache_dvm_set_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type, slave_port_id {
      ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::DVMMESSAGE,
                                                                                             svt_axi_transaction::DVMCOMPLETE}) &&
                                                 (!binsof(cache_type) intersect {4'b0010});
      ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                 (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                             4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                 (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arcache_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_arcache_dvm_unset_barrier_set

This covergroup captures coherant read xact_type, cache signal and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
cache_type : Captures transaction cache type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arcache : Crosses coverpoints coherent_read_xact_type and cache_type and slave_port_id

covergroup trans_cross_ace_arsnoop_arcache_dvm_unset_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arcache : cross coherent_read_xact_type, cache_type, slave_port_id {
      ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::DVMMESSAGE,
                                                                                             svt_axi_transaction::DVMCOMPLETE}) &&
                                                 (!binsof(cache_type) intersect {4'b0010});
      ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                 (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                 (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_set

This Covergroup captures coherant read xact_type,domain_type and slave_port_id for read transaction. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_ardomain_enable set to 1 , barrier_enable set to 1 & dvm_enable can be 0 or 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures transaction cache type

Cross coverpoints:

arsnoop_ardomain : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_unset

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures transaction cache type

Cross coverpoints:

arsnoop_ardomain : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_ace_lite_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_set

This Covergroup captures coherant read xact_type,domain_type and cache signal for read transaction. It is constructed and sampled when when interface_type is ACE_LITE,trans_cross_ace_arsnoop_ardomain_arcache_enable set to 1 , dvm_enable can be 0 or 1 & barrier_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache_type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses cover points coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
      ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                     ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_unset

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache_type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses cover points coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_ace_lite_barrier_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                            ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_def

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_def

This Covergroup captures coherant read xact_type,domain_type and cache signal for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_arcache_enable set to 1 , dvm_enable and barrier_enable is set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache_type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses cover points coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_def;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
         arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
         ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READBARRIER,
                                                  svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                  (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
             ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                     ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_set

This covergroup captures coherant read xact_type,domain_type and cache signal for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_ardomain_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses coverpoints coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READBARRIER,
                                                    svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE}) &&
                                                   (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                                   4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                   (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                  4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_unset

This covergroup captures coherant read xact_type, domain_type and cache signal for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_ardomain_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses coverpoints coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_dvm_set_barrier_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READBARRIER,
                                                    svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE}) &&
                                                   (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                                   4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                   (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                  4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_arcache_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_arcache_dvm_unset_barrier_set

This covergroup captures coherant read xact_type, domain_type and cache signal for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_ardomain_arcache_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

arsnoop_ardomain_arcache : Crosses coverpoints coherent_read_xact_type and domain_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_arcache_dvm_unset_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain_arcache : cross coherent_read_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
            ignore_bins Ignore_invalid_cache_barrier = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READBARRIER,
                                                    svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE}) &&
                                                   (!binsof(cache_type) intersect {4'b0010});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                                   4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_read_xact_type.coherent_readnosnoop_xact) &&
                                                   (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                  4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_def

Covergroup: trans_cross_ace_arsnoop_ardomain_def

This Covergroup captures coherant read xact_type,domain_type and slave_port_id for read transaction. It is constructed and sampled when trans_cross_ace_arsnoop_ardomain_enable set to 1, barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
domain_type : Captures transaction cache type

Cross coverpoints:

arsnoop_ardomain : Crosses cover points coherent_read_xact_type and cache_type

covergroup trans_cross_ace_arsnoop_ardomain_def(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE,svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
        ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANINVALID,
                                            svt_axi_transaction::MAKEINVALID,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_set

This covergroup captures coherant read xact_type, domain_type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_ardomain_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures transaction domain type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_ardomain : Crosses coverpoints coherent_read_xact_type and domain_type and slave_port_id

covergroup trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type, slave_port_id {
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures transaction domain type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_ardomain : Crosses coverpoints coherent_read_xact_type and domain_type and slave_port_id

covergroup trans_cross_ace_arsnoop_ardomain_dvm_set_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type, slave_port_id {
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_ardomain_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_ardomain_dvm_unset_barrier_set

This covergroup captures coherant read xact_type, domain_type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_ardomain_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
domain_type : Captures transaction domain type
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_ardomain : Crosses coverpoints coherent_read_xact_type and domain_type and slave_port_id

covergroup trans_cross_ace_arsnoop_ardomain_dvm_unset_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_ardomain : cross coherent_read_xact_type, domain_type, slave_port_id {
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                   svt_axi_transaction::OUTERSHAREABLE});
      ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::READONCE, svt_axi_transaction::READSHARED,
                                                    svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                    svt_axi_transaction::READUNIQUE, svt_axi_transaction::CLEANUNIQUE,
                                                    svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::DVMCOMPLETE,
                                                    svt_axi_transaction::DVMMESSAGE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                   {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANINVALID,
                                                    svt_axi_transaction::MAKEINVALID, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_ace_lite_barrier_set

Covergroup: trans_cross_ace_arsnoop_arlen_ace_lite_barrier_set

This Covergroup captures coherant read xact_type,burst_length and slave_port_id for read transaction. It is constructed and sampled when interface_type is ACE_LITE ,trans_cross_ace_arsnoop_arlen_enable is set to 1 , dvm_enable is set to 1 or 0 & barrier_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_length: Captures transaction burst length

Cross coverpoints:

arsnoop_arlen : Crosses cover points coherent_read_xact_type and burst_length

covergroup trans_cross_ace_arsnoop_arlen_ace_lite_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arlen : cross coherent_read_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length = binsof(burst_length) &&
                                                   (!binsof(coherent_read_xact_type)
                                                     intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                              (binsof(coherent_read_xact_type) intersect
                                                 {svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                  svt_axi_transaction::READSHARED,svt_axi_transaction::READUNIQUE,
                                                  svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST,svt_axi_transaction::CLEANUNIQUE,
                                                  svt_axi_transaction::CLEANINVALID,svt_axi_transaction::MAKEINVALID,
                                                  svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}
                                              );
       ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                   svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_ace_lite_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arlen_ace_lite_barrier_unset

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_length: Captures transaction burst length

Cross coverpoints:

arsnoop_arlen : Crosses cover points coherent_read_xact_type and burst_length

covergroup trans_cross_ace_arsnoop_arlen_ace_lite_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arlen : cross coherent_read_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length = binsof(burst_length) &&
                                                   (!binsof(coherent_read_xact_type)
                                                     intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                              (binsof(coherent_read_xact_type) intersect
                                                 {svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                  svt_axi_transaction::READSHARED,svt_axi_transaction::READUNIQUE,
                                                  svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST,svt_axi_transaction::CLEANUNIQUE,
                                                  svt_axi_transaction::CLEANINVALID,svt_axi_transaction::MAKEINVALID,
                                                  svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}
                                              );
        ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                   svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_def

Covergroup: trans_cross_ace_arsnoop_arlen_def

This Covergroup captures coherant read xact_type,burst_length and slave_port_id for read transaction. It is constructed and sampled when interface_type is not ACE_LITE & trans_cross_ace_arsnoop_arlen_enable is set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_length: Captures transaction burst length

Cross coverpoints:

arsnoop_arlen : Crosses cover points coherent_read_xact_type and burst_length

covergroup trans_cross_ace_arsnoop_arlen_def(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arlen : cross coherent_read_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length = binsof(burst_length) &&
                                                   (!binsof(coherent_read_xact_type)
                                                     intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                              (binsof(coherent_read_xact_type) intersect
                                                 {svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                  svt_axi_transaction::READSHARED,svt_axi_transaction::READUNIQUE,
                                                  svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST,svt_axi_transaction::CLEANUNIQUE,
                                                  svt_axi_transaction::CLEANINVALID,svt_axi_transaction::MAKEINVALID,
                                                  svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}
                                              );
       ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                   svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_arlen_dvm_set_barrier_set

This covergroup captures coherant read xact_type, burst_length and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arlen_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_length : Captures transaction burst length
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arlen : Crosses coverpoints coherent_read_xact_type and burst_length and slave_port_id

covergroup trans_cross_ace_arsnoop_arlen_dvm_set_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arlen : cross coherent_read_xact_type, burst_length, slave_port_id {
      ignore_bins Ignore_invalid_length = binsof(burst_length) && (!binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                                 (binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE,
                                                     svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST, svt_axi_transaction::CLEANUNIQUE,
                                                     svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID,
                                                     svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::WRITELINEUNIQUE});
       ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                     svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_arlen_dvm_set_barrier_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_length : Captures transaction burst length
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arlen : Crosses coverpoints coherent_read_xact_type and burst_length and slave_port_id

covergroup trans_cross_ace_arsnoop_arlen_dvm_set_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arlen : cross coherent_read_xact_type, burst_length, slave_port_id {
      ignore_bins Ignore_invalid_length = binsof(burst_length) && (!binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                                 (binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE,
                                                     svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST, svt_axi_transaction::CLEANUNIQUE,
                                                     svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID,
                                                     svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::WRITELINEUNIQUE});
       ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                     svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arlen_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_arlen_dvm_unset_barrier_set

This covergroup captures coherant read xact_type, burst_length and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arlen_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_length : Captures transaction burst length
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arlen : Crosses coverpoints coherent_read_xact_type and burst_length and slave_port_id

covergroup trans_cross_ace_arsnoop_arlen_dvm_unset_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_arlen : cross coherent_read_xact_type, burst_length, slave_port_id {
      ignore_bins Ignore_invalid_length = binsof(burst_length) && (!binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
         ignore_bins Ig_len_for_CLsize_coh_txn = (binsof(burst_length) intersect {[2:3],[5:7],[9:15]}) &&
                                                 (binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                     svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE,
                                                     svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST, svt_axi_transaction::CLEANUNIQUE,
                                                     svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID,
                                                     svt_axi_transaction::MAKEUNIQUE, svt_axi_transaction::WRITELINEUNIQUE});
       ignore_bins Ig_len_for_evict_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::EVICT,
                                                     svt_axi_transaction::DVMCOMPLETE, svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dweq_1024

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width 1024 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_1024

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 1024 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_128

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 128 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_16

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_256

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 256 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_32

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when interface_type is ACE_LITE ,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_512

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 512 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_64

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 64 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable & barrier_enable set to 1.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_set_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dweq_1024

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_1024

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_128

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_16

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 16 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable set to 1 & barrier_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_256

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_32

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_arsnoop_arsize_enable set to 1 & barrier_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_512

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_64

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_ace_lite_barrier_unset_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_def_dweq_1024

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 256 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_1024

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_128

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 128 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_16

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 16 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_256

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_32

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_512

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 512 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_def_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_def_dwlt_64

This Covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 64 bits. It is constructed and sampled when trans_cross_ace_arsnoop_arsize_enable is set to 1 ,barrier_enable & dvm_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
burst_size: Captures transaction burst size

Cross coverpoints:

arsnoop_arsize : Crosses cover points coherent_read_xact_type and burst_size

covergroup trans_cross_ace_arsnoop_arsize_def_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) &&
                                          (!binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                        svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dweq_1024

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width 1024 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_1024

This covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 1024 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_128

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 128 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_16

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 16 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_256

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 256 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_32

This covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_512

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 512 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_64

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 64 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_set_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect { svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dweq_1024

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_1024

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 1024 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_128

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_16

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_256

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_32

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_512

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_64

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_set_barrier_unset_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dweq_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dweq_1024

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width 1024 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dweq_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_1024

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_1024

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 1024 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_1024(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_128

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_128

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 128 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_128(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_16

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_16

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 16 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_16(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_256

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_256

This covergroup captures coherant read xact_type,burst_size and slave_port_id for read transaction for data width less than 256 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_256(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_32

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_32

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_32(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_512

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_512

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 512 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_512(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_64

Covergroup: trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_64

This covergroup captures coherant read xact_type, burst_size and slave_port_id for read transaction for data width less than 64 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is ACE_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_arsize_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
burst_size : Captures transaction burst size
slave_port_id : Captures transaction slave port id

Cross coverpoints:

arsnoop_arsize : Crosses coverpoints coherent_read_xact_type and burst_size and slave_port_id

covergroup trans_cross_ace_arsnoop_arsize_dvm_unset_barrier_set_dwlt_64(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
               arsnoop_arsize : cross coherent_read_xact_type, burst_size, slave_port_id {
      ignore_bins Ignore_invalid_size = binsof(burst_size) && (!binsof(coherent_read_xact_type) intersect
                                                {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE});
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMCOMPLETE,
                                                 svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::READBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def

This Covergroup captures coherant read xact_type ,initial and final cacheline state for read transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_WRITE_ONLY & trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_enable is set 1 and dvm_enable ,barrier_enable and speculative_read_enable set to 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state ,
                                                        final_cache_line_state {
       ignore_bins Ignore_readnosnoop_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READNOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID,svt_axi_transaction::UNIQUECLEAN}));
       ignore_bins Ignore_readonce_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_readclean_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READCLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readnotshareddirty_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY,
                                                    svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readshared_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READSHARED}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY,
                                                    svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY}));
       ignore_bins Ignore_readunique_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleanunique_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY})) ;
       ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::MAKEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN,
                                                     svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY})) ;
        ignore_bins Ignore_cleanshared_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}));
      ignore_bins Ignore_invalid_initial_state = ((binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::CLEANINVALID,svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::CLEANINVALID}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ;
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::MAKEINVALID}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ;
       ignore_bins Ignore_speculative_initial_states = ((binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::READNOSNOOP,svt_axi_transaction::READONCE,
                                                       svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                       svt_axi_transaction::READSHARED,svt_axi_transaction::READUNIQUE}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID}))||
                                                     ((binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY})) ||
                                                    ((binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                      {svt_axi_transaction::READBARRIER,svt_axi_transaction::DVMCOMPLETE,
                                                       svt_axi_transaction::DVMMESSAGE};
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def_speculative_read_enable

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def_speculative_read_enable

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_def_speculative_read_enable;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_readnosnoop_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_readonce_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
                       ignore_bins Ignore_readclean_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readnotshareddirty_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
        ignore_bins Ignore_readshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
                                                      ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
       ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_readnosnoop_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN}));
       ignore_bins Ignore_readonce_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_readclean_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readnotshareddirty_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readshared_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY}));
       ignore_bins Ignore_readunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::SHAREDDIRTY}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_speculative_initial_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE,
                                                            svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                            svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
       ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set_speculative_read_enable

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set_speculative_read_enable

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_set_speculative_read_enable;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
      ignore_bins Ignore_readnosnoop_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN,
                                                            svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_readonce_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readclean_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readnotshareddirty_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY,svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
       ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
       ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
       ignore_bins Ignore_readnosnoop_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READNOSNOOP}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN}));
       ignore_bins Ignore_readonce_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READONCE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_readclean_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READCLEAN}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readnotshareddirty_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                             svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readshared_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READSHARED}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                             svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY}));
       ignore_bins Ignore_readunique_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::READUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::SHAREDCLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUECLEAN})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::SHAREDDIRTY}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::MAKEUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                             svt_axi_transaction::SHAREDDIRTY}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::CLEANINVALID}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                            {svt_axi_transaction::MAKEINVALID}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                            {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_speculative_initial_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE,
                                                            svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                            svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                       (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
       ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                       (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY})) ||
                                                       ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID,svt_axi_transaction::MAKEINVALID}) &&
                                                       (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 0;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset_speculative_read_enable

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset_speculative_read_enable

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_set_barrier_unset_speculative_read_enable;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
       ignore_bins Ignore_readnosnoop_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN,
                                                            svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_readonce_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readclean_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readnotshareddirty_states = (((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                           svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readshared_states = (((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                           svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readunique_states = (((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID})));
       ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                           svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY,
                                                           svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                          {svt_axi_transaction::CLEANINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                          {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
       ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
       ignore_bins Ignore_readnosnoop_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN}));
       ignore_bins Ignore_readonce_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_readclean_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readnotshareddirty_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::SHAREDCLEAN}));
       ignore_bins Ignore_readshared_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY}));
       ignore_bins Ignore_readunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
      ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}));
      ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
      ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
      ignore_bins Ignore_speculative_initial_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP, svt_axi_transaction::READONCE,
                                                            svt_axi_transaction::READCLEAN, svt_axi_transaction::READNOTSHAREDDIRTY,
                                                            svt_axi_transaction::READSHARED, svt_axi_transaction::READUNIQUE}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})));
      ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                            svt_axi_transaction::DVMMESSAGE};
       ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
     ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set_speculative_read_enable

Covergroup: trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set_speculative_read_enable

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state

Cross coverpoints:

arsnoop_cacheinitialstate_cachefinalstate : Crosses coverpoints coherent_read_xact_type and initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_arsnoop_cacheinitialstate_cachefinalstate_dvm_unset_barrier_set_speculative_read_enable;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     arsnoop_cacheinitialstate_cachefinalstate : cross coherent_read_xact_type, initial_cache_line_state, final_cache_line_state {
       ignore_bins Ignore_readnosnoop_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN,
                                                            svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_readonce_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READONCE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
                       ignore_bins Ignore_readclean_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READCLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readnotshareddirty_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
        ignore_bins Ignore_readshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READSHARED}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})));
       ignore_bins Ignore_readunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})));
       ignore_bins Ignore_cleanunique_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN, svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
                                                      ignore_bins Ignore_makeunique_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID, svt_axi_transaction::SHAREDCLEAN,
                                                            svt_axi_transaction::SHAREDDIRTY, svt_axi_transaction::UNIQUEDIRTY,
                                                            svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY}));
       ignore_bins Ignore_cleaninvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_makeinvalid_states = ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::MAKEINVALID}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}));
       ignore_bins Ignore_invalid_xact_types = binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::READBARRIER, svt_axi_transaction::DVMCOMPLETE,
                                                             svt_axi_transaction::DVMMESSAGE};
        ignore_bins Ignore_cleanshared_states = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::SHAREDCLEAN}) &&
                                                      (!binsof(final_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUECLEAN, svt_axi_transaction::SHAREDCLEAN})));
      ignore_bins Ignore_invalid_initial_state = (((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANSHARED, svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::UNIQUEDIRTY, svt_axi_transaction::SHAREDDIRTY})) ||
                                                      ((binsof(coherent_read_xact_type) intersect
                                                           {svt_axi_transaction::CLEANINVALID, svt_axi_transaction::MAKEINVALID}) &&
                                                      (!binsof(initial_cache_line_state) intersect
                                                           {svt_axi_transaction::INVALID})));
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_coh_rresp_def

Covergroup: trans_cross_ace_arsnoop_coh_rresp_def

This Covergroup captures coherant read xact_type,response type and slave_port_id for read transaction. It is constructed and sampled when interface type is not ACE_LITE and AXI_WRITE_ONLY, trans_cross_ace_arsnoop_coh_rresp_enable set to 1 and dvm_enable & barrier_enable set to 0.

Coverpoints:

coherent_read_xact_type: Captures coherent read transaction
coh_rresp : Captures read coherent response

Cross coverpoints:

arsnoop_coh_rresp : Crosses cover points coherent_read_xact_type and coh_rresp

covergroup trans_cross_ace_arsnoop_coh_rresp_def(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
     coh_rresp : coverpoint cov_coherent_rresp iff(cov_coherent_rresp_flag){
    bins coherent_rresp_shared_clean = {svt_axi_transaction::SHARED_CLEAN};
    bins coherent_rresp_shared_dirty = {svt_axi_transaction::SHARED_DIRTY};
    bins coherent_rresp_unique_clean = {svt_axi_transaction::UNIQUE_CLEAN};
    bins coherent_rresp_unique_dirty = {svt_axi_transaction::UNIQUE_DIRTY};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_coh_rresp : cross coherent_read_xact_type, coh_rresp , slave_port_id{
      ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coherent_read_xact_type) intersect {
                                                   svt_axi_transaction::READNOSNOOP,
                                                   svt_axi_transaction::CLEANUNIQUE,svt_axi_transaction::MAKEUNIQUE,
                                                   svt_axi_transaction::MAKEINVALID,svt_axi_transaction::READBARRIER,
                                                   svt_axi_transaction::CLEANINVALID} &&
                                                 !binsof(coh_rresp) intersect {
                                                   svt_axi_transaction::UNIQUE_CLEAN };
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(coherent_read_xact_type) intersect {
                                                   svt_axi_transaction::READUNIQUE} &&
                                                 binsof(coh_rresp) intersect {
                                                   svt_axi_transaction::SHARED_CLEAN,svt_axi_transaction::SHARED_DIRTY};
        ignore_bins Ignore_invalid_rresp_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOTSHAREDDIRTY} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_dvm_xact_type = binsof(coherent_read_xact_type) intersect {
                                                 svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE};
                                            ignore_bins Ignore_invalid_rresp_ud_sd = binsof(coherent_read_xact_type) intersect {
                                                   svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHAREDPERSIST,
                                                   svt_axi_transaction::READCLEAN,svt_axi_transaction::CLEANSHARED} &&
                                                 binsof(coh_rresp) intersect {
                                                   svt_axi_transaction::UNIQUE_DIRTY,svt_axi_transaction::SHARED_DIRTY};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_set

Covergroup: trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_set

This covergroup captures coherant read xact_type, response type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_coh_rresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 1

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
coh_rresp : Captures read coherent response
slave_port_id : Captures slave port id

Cross coverpoints:

arsnoop_coh_rresp : Crosses coverpoints coherent_read_xact_type and coh_rresp and slave_port_id

covergroup trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     coh_rresp : coverpoint cov_coherent_rresp iff(cov_coherent_rresp_flag){
    bins coherent_rresp_shared_clean = {svt_axi_transaction::SHARED_CLEAN};
    bins coherent_rresp_shared_dirty = {svt_axi_transaction::SHARED_DIRTY};
    bins coherent_rresp_unique_clean = {svt_axi_transaction::UNIQUE_CLEAN};
    bins coherent_rresp_unique_dirty = {svt_axi_transaction::UNIQUE_DIRTY};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_coh_rresp : cross coherent_read_xact_type, coh_rresp, slave_port_id {
      ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,
                                                                                             svt_axi_transaction::CLEANUNIQUE, svt_axi_transaction::MAKEUNIQUE,
                                                                                             svt_axi_transaction::MAKEINVALID, svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::CLEANINVALID} &&
                                                  !binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_CLEAN};
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READUNIQUE} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_CLEAN, svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_invalid_rresp_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOTSHAREDDIRTY} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_dvm_xact_type = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
        ignore_bins Ignore_invalid_rresp_ud_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::CLEANSHAREDPERSIST,
                                                                                             svt_axi_transaction::READCLEAN, svt_axi_transaction::CLEANSHARED} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_DIRTY, svt_axi_transaction::SHARED_DIRTY};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_unset

Covergroup: trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_unset

This covergroup captures coherant read xact_type, response type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_coh_rresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: barrier_enable = 0.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
coh_rresp : Captures read coherent response
slave_port_id : Captures slave port id

Cross coverpoints:

arsnoop_coh_rresp : Crosses coverpoints coherent_read_xact_type and coh_rresp and slave_port_id

covergroup trans_cross_ace_arsnoop_coh_rresp_dvm_set_barrier_unset(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
     bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    option.weight = 0;
    type_option.weight = 0;
  }
     coh_rresp : coverpoint cov_coherent_rresp iff(cov_coherent_rresp_flag){
    bins coherent_rresp_shared_clean = {svt_axi_transaction::SHARED_CLEAN};
    bins coherent_rresp_shared_dirty = {svt_axi_transaction::SHARED_DIRTY};
    bins coherent_rresp_unique_clean = {svt_axi_transaction::UNIQUE_CLEAN};
    bins coherent_rresp_unique_dirty = {svt_axi_transaction::UNIQUE_DIRTY};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_coh_rresp : cross coherent_read_xact_type, coh_rresp, slave_port_id{
      ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,
                                                                                             svt_axi_transaction::CLEANUNIQUE, svt_axi_transaction::MAKEUNIQUE,
                                                                                             svt_axi_transaction::MAKEINVALID, svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::CLEANINVALID} &&
                                                  !binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_CLEAN};
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READUNIQUE} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_CLEAN, svt_axi_transaction::SHARED_DIRTY};
         ignore_bins Ignore_invalid_rresp_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOTSHAREDDIRTY} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_dvm_xact_type = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
        ignore_bins Ignore_invalid_rresp_ud_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::CLEANSHAREDPERSIST,
                                                                                             svt_axi_transaction::READCLEAN,svt_axi_transaction::CLEANSHARED} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_DIRTY, svt_axi_transaction::SHARED_DIRTY};
      option.weight = 1;
    }
    option.per_instance = 1;
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_arsnoop_coh_rresp_dvm_unset_barrier_set

Covergroup: trans_cross_ace_arsnoop_coh_rresp_dvm_unset_barrier_set

This covergroup captures coherant read xact_type, response type and slave_port_id for read transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is !ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_arsnoop_coh_rresp_enable = 1 svt_axi_port_configuration :: dvm_enable = 0 svt_axi_port_configuration :: barrier_enable = 1.

Coverpoints:

coherent_read_xact_type : Captures coherent read transaction
coh_rresp : Captures read coherent response
slave_port_id : Captures slave port id

Cross coverpoints:

arsnoop_coh_rresp : Crosses coverpoints coherent_read_xact_type and coh_rresp and slave_port_id

covergroup trans_cross_ace_arsnoop_coh_rresp_dvm_unset_barrier_set(int num_slaves);
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     coh_rresp : coverpoint cov_coherent_rresp iff(cov_coherent_rresp_flag){
    bins coherent_rresp_shared_clean = {svt_axi_transaction::SHARED_CLEAN};
    bins coherent_rresp_shared_dirty = {svt_axi_transaction::SHARED_DIRTY};
    bins coherent_rresp_unique_clean = {svt_axi_transaction::UNIQUE_CLEAN};
    bins coherent_rresp_unique_dirty = {svt_axi_transaction::UNIQUE_DIRTY};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     arsnoop_coh_rresp : cross coherent_read_xact_type, coh_rresp, slave_port_id{
      ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOSNOOP,
                                                                                             svt_axi_transaction::CLEANUNIQUE, svt_axi_transaction::MAKEUNIQUE,
                                                                                             svt_axi_transaction::MAKEINVALID, svt_axi_transaction::READBARRIER,
                                                                                             svt_axi_transaction::CLEANINVALID} &&
                                                  !binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_CLEAN};
       ignore_bins Ignore_invalid_rresp_sc_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READUNIQUE} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_CLEAN, svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_invalid_rresp_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READNOTSHAREDDIRTY} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::SHARED_DIRTY};
       ignore_bins Ignore_dvm_xact_type = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::DVMMESSAGE, svt_axi_transaction::DVMCOMPLETE};
        ignore_bins Ignore_invalid_rresp_ud_sd = binsof(coherent_read_xact_type) intersect {svt_axi_transaction::READONCE, svt_axi_transaction::CLEANSHAREDPERSIST,
                                                                                             svt_axi_transaction::READCLEAN, svt_axi_transaction::CLEANSHARED} &&
                                                  binsof(coh_rresp) intersect {svt_axi_transaction::UNIQUE_DIRTY, svt_axi_transaction::SHARED_DIRTY};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awdomain_awbarrier_memory_sync

Covergroup: trans_cross_ace_awdomain_awbarrier_memory_sync

This Covergroup captures barrier_type and domain_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_memory_sync_enable

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type MEMORY_BARRIER & SYNC_BARRIER with awdomain

As barrier types are memory & sync therefore, ignoring bins intersect with NORMAL_ACCESS_RESPECT_BARRIER & NORMAL_ACCESS_IGNORE_BARRIER and ignoring all other non-writebarrier bins.

covergroup trans_cross_ace_awdomain_awbarrier_memory_sync;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_WRITE_XACT_TYPE
    coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
      option.weight = 0;
    }
    // Only MEMORY_BARRIER and SYNC_BARRIER are being covered, so we need to use only the BARRIER_SET macro
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_BARRIER_TYPE
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     awdomain_awbarrier_memory_sync : cross coherent_write_xact_type, barrier_type, domain_type {
       ignore_bins ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins ignore_non_write_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awdomain_awbarrier_respect_ignore_ace_lite

Covergroup : trans_cross_ace_awdomain_awbarrier_respect_ignore_ace_lite

This Covergroup captures coherant write xact_type and barrier_type for write transaction. It is constructed and sampled when interface_type is ACE_LITE & trans_cross_ace_awdomain_awbarrier_respect_ignore_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures non write barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with awdomain

As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are WRITEBARRIER with Memory & Sync

covergroup trans_cross_ace_awdomain_awbarrier_respect_ignore_ace_lite;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     awdomain_awbarrier_respect_ignore : cross coherent_write_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_write_barrier = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_no_writeevict

Covergroup : trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_no_writeevict

This Covergroup captures coherant write xact_type and barrier_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_respect_ignore_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures non write barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with awdomain

As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are WRITEBARRIER with Memory & Sync

covergroup trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_no_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     awdomain_awbarrier_respect_ignore : cross coherent_write_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_write_barrier = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_writeevict

Covergroup : trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_writeevict

This Covergroup captures coherant write xact_type and barrier_type for write transaction. It is constructed and sampled when trans_cross_ace_awdomain_awbarrier_respect_ignore_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures non write barrier (all other coherent transactions) as its normal access with respect or ignore barrier
domain_type : Captures domain type

Cross coverpoints:

awbarrier_awdomain : Crosses cover points write transaction of certain barrier_type NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER with awdomain

As barrier type with respect & ignore barriers are normal coherent access therefore, ignoring bins are WRITEBARRIER with Memory & Sync

covergroup trans_cross_ace_awdomain_awbarrier_respect_ignore_not_ace_lite_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     awdomain_awbarrier_respect_ignore : cross coherent_write_xact_type, barrier_type, domain_type {
       ignore_bins ignore_memory_sync_barrier = (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      ignore_bins ignore_write_barrier = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awprot_awbarrier_memory_sync

Covergroup: trans_cross_ace_awprot_awbarrier_memory_sync

It is constructed and sampled when trans_cross_ace_awprot_awbarrier_memory_sync_enable is asserted.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier
prot_type : Captures transaction protection type

Cross coverpoints:

awprot_awbarrier_memory_sync: Crosses cover points write transaction of barrier_type MEMORY_BARRIER & SYNC_BARRIER with awprot

The following bins are ignored:

bins that interset NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER
bins that intersect transaction types other than WRITEBARRIER
Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_ace_awprot_awbarrier_memory_sync;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_WRITE_XACT_TYPE
    coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    // Only MEMORY_BARRIER and SYNC_BARRIER are being covered, so we need to use only the BARRIER_SET macro
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_BARRIER_TYPE
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    awprot_awbarrier_memory_sync : cross coherent_write_xact_type, barrier_type, prot_type {
       ignore_bins ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
      ignore_bins ignore_non_write_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_awbar_set

Covergroup:trans_cross_ace_awsnoop_ace_lite_barrier_awbar_set

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when interface_type is ACE_LITE , trans_cross_ace_awsnoop_awbar_enable barrier_enableis set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_awbar_set;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins Ignore_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_awburst_axi3_ace

Covergroup:trans_cross_ace_awsnoop_ace_lite_barrier_awburst_axi3_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is AXI_LITE and cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst : Crosses cover points coherent_write_xact_type ,burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_awdomain

Covergroup:trans_cross_ace_awsnoop_ace_lite_barrier_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE,trans_cross_ace_awsnoop_awdomain_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_awlen_ace

Covergroup: trans_cross_ace_awsnoop_ace_lite_barrier_awlen_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_bresp_all

Covergroup:trans_cross_ace_awsnoop_ace_lite_barrier_bresp_all

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE & trans_cross_ace_awsnoop_bresp_enable, barrier_enable & exclusive_access_enable is set to 1 .

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_barrier_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_ace_lite_barrier_bresp_no_exclusive

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_ace_lite_barrier_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_awbar_unset

Covergroup:trans_cross_ace_awsnoop_ace_lite_no_barrier_awbar_unset

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when interface_type is ACE_LITE & trans_cross_ace_awsnoop_awbar_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_awbar_unset;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_awburst_axi3_ace

Covergroup:trans_cross_ace_awsnoop_ace_lite_no_barrier_awburst_axi3_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is AXI_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst : Crosses cover points coherent_write_xact_type ,burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_awdomain

Covergroup:trans_cross_ace_awsnoop_ace_lite_no_barrier_awdomain

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_awlen_ace

Covergroup: trans_cross_ace_awsnoop_ace_lite_no_barrier_awlen_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_all

Covergroup:trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_all

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_no_exclusive

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_ace_lite_no_barrier_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_ace_lite_barrier

Covergroup: trans_cross_ace_awsnoop_awaddr_ace_lite_barrier

This Covergroup captures coherant write transaction and address It is constructed and sampled when interface type is ACE_LITE and barrier_enable is 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_ace_lite_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_write_xact_type.coherent_writebarrier_xact) && binsof(addr);
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_ace_lite_no_barrier

Covergroup: trans_cross_ace_awsnoop_awaddr_ace_lite_no_barrier

This Covergroup captures coherant write transaction and address It is constructed and sampled when interface type is ACE_LITE and barrier_enable is 0.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_ace_lite_no_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_not_ace_lite_barrier_no_writeevict

Covergroup: trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_writeevict

This Covergroup captures coherant write transaction and address It is constructed and sampled when writeevict_enale and barrier_enable is set to 1 and writeevict_enable is 0 .

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_not_ace_lite_barrier_no_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_write_xact_type.coherent_writebarrier_xact) && binsof(addr);
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_not_ace_lite_barrier_writeevict

Covergroup: trans_cross_ace_awsnoop_awaddr_not_ace_lite_barrier_writeevict

This Covergroup captures coherant write transaction and address It is constructed and sampled when writeevict_enale and barrier_enable and writeevict_enable is set to 1 .

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_not_ace_lite_barrier_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ignore_invalid_addr = binsof(coherent_write_xact_type.coherent_writebarrier_xact) && binsof(addr);
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_no_writeevict

Covergroup: trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_no_writeevict

This Covergroup captures coherant write transaction and address It is constructed and sampled when writeevict_enale and barrier_enable is set to 0.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_no_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_writeevict

Covergroup: trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_writeevict

This Covergroup captures coherant write transaction and address It is constructed and sampled when writeevict_enale and barrier_enable is set to 0 and writeevict_enable is 1 .

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
addr : Captures transaction write address

Cross coverpoints:

awsnoop_awaddr : Crosses cover points coherent_write_xact_type and addr

covergroup trans_cross_ace_awsnoop_awaddr_not_ace_lite_no_barrier_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    awsnoop_awaddr : cross coherent_write_xact_type, addr {
      ignore_bins Ig_burst_for_dvm_barrier = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_ace_lite_barrier

Covergroup: trans_cross_ace_awsnoop_awcache_ace_lite_barrier

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when interface_type is ACE_LITE & barrier_enable is 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_ace_lite_barrier(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
           ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_ace_lite_no_barrier

Covergroup: trans_cross_ace_awsnoop_awcache_ace_lite_no_barrier

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when interface_type is ACE_LITE & barrier_enable is 0.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_ace_lite_no_barrier(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_no_writeevict

Covergroup: trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_no_writeevict

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_no_writeevict(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_writeevict

Covergroup: trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_writeevict

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_not_ace_lite_barrier_writeevict(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_no_writeevict

Covergroup: trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_no_writeevict

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_no_writeevict(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_writeevict

Covergroup: trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_writeevict

This Covergroup captures coherant write xact_type,cache signal and slave_port_id . It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awcache : Crosses cover points coherent_write_xact_type and cache_type

covergroup trans_cross_ace_awsnoop_awcache_not_ace_lite_no_barrier_writeevict(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awcache : cross coherent_write_xact_type, cache_type , slave_port_id{
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_barrier

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_barrier

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when interface_type is ACE_LITE ,trans_cross_ace_awsnoop_awdomain_awcache_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
      ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
              option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_no_barrier

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_no_barrier

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when interface_type is ACE_LITE & trans_cross_ace_awsnoop_awdomain_awcache_enable, barrier_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_ace_lite_no_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                    option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_no_writeevict

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_no_writeevict

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_awcache_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_no_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                           option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_writeevict

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_writeevict

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_barrier_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache_barrier = binsof(coherent_write_xact_type.coherent_writebarrier_xact) &&
                                                 !binsof(cache_type) intersect {4'b0010};
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                    option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_no_writeevict

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_no_writeevict

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_awcache_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_no_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                           option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_writeevict

Covergroup:trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_writeevict

This Covergroup captures coherant write xact_type,domain and cache type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_awcache_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type
cache_type : Captures cache type

Cross coverpoints:

awsnoop_awdomain_awcache : Crosses cover points coherent_write_xact_type and domain_type and cache_type

covergroup trans_cross_ace_awsnoop_awdomain_awcache_not_ace_lite_no_barrier_writeevict;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awdomain_awcache : cross coherent_write_xact_type, domain_type, cache_type {
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_invalid_cache = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                         (!binsof(cache_type) intersect {4'b0010,4'b0011,4'b0110,4'b0111,
                                                                         4'b1010,4'b1011,4'b1110,4'b1111});
       ignore_bins Ig_device_nonshare_cache = binsof(coherent_write_xact_type.coherent_writenosnoop_xact) &&
                                            (binsof(cache_type) intersect {4'b0000,4'b0001});
       ignore_bins Ig_device_non_system_shareable = (binsof(cache_type) intersect {4'b0000,4'b0001}) &&
                                                   (!binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ig_cacheable_system_shareable = (binsof(cache_type) intersect {4'b0110,4'b0111,
                                                                                 4'b1010,4'b1011,4'b1110,4'b1111}) &&
                                                  (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
                    option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dweq_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width 1024. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 1024. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128 It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16 It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256 It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_16

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512 It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
              awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64 It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_barrier_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dweq_1024

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_1024

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_32

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 32. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64. It is constructed and sampled when interface_type is ACE_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_ace_lite_no_barrier_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dweq_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_32

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 32. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_no_writeevict_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dweq_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_32

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 32. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_barrier_writeevict_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dweq_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type,burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16. It is constructed and sampled when cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type ,burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_32

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 32. It is constructed and sampled when cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64. It is constructed and sampled when cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type,burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_no_writeevict_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dweq_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dweq_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dweq_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_1024

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_1024

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 1024. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_1024(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_128

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_128

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 128. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_128(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_16

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_16

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 16. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_16(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_256

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_256

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 256. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_256(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_32

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_32

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 32. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_32(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_512

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_512

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 512. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_512(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size, slave_port_id {
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_64

Covergroup : trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_64

This Covergroup captures coherant xact type,burst_type and slave_port_id for data width less than 64. It is constructed and sampled when cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_size: Captures transaction burst sizes

Cross coverpoints:

awsnoop_awsize : Crosses cover points coherent_write_xact_type, burst_size and slave_port_id

covergroup trans_cross_ace_awsnoop_awsize_not_ace_lite_no_barrier_writeevict_dwlt_64(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
         awsnoop_awsize : cross coherent_write_xact_type, burst_size , slave_port_id{
                 ignore_bins Ignore_invalid_size_all = binsof(burst_size) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT };
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awbar_set

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awbar_set

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awbar_set;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins Ignore_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awburst_axi3_ace

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awburst_axi3_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is not AXI_LITE and cov_trans_cross_slave_port_id_enable & barrier_enbale is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst_ : Crosses cover points coherent_write_xact_type, burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awdomain

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awlen_ace

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awlen_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is not ACE_LITE and cov_trans_cross_slave_port_id_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_all

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_all

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable,barrier_enable & exclusive_access_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_no_exclusive

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_cacheinitialstate_cachefinalstate

This Covergroup captures coherant read xact_type ,initial and final cacheline state for write transaction. It is constructed and sampled when interface_type is not ACE_LITE and interface_category is not AXI_READ_ONLY & trans_cross_ace_awsnoop_cacheinitialstate_cachefinalstate_enable set & barrier_enable set to 1 writeevict_enable to 0.

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_cacheinitialstate_cachefinalstate;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     awsnoop_cacheinitialstate_cachefinalstate : cross coherent_write_xact_type, initial_cache_line_state ,
                                                        final_cache_line_state {
              ignore_bins Ignore_writenosnoop_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}));
        ignore_bins Ignore_writeuniqueorline_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins Ignore_writeback_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEBACK}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeevict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (!binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) ) ||
                                                ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeclean_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins evict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::EVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_invalid_initial_state = ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITENOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY}))|| ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}))||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITECLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN,
                                                       svt_axi_transaction::UNIQUECLEAN})) ||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::EVICT}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::UNIQUEDIRTY,
                                                       svt_axi_transaction::SHAREDDIRTY}));
          ignore_bins Ignore_invalid_xact_types = binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awbar_set

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awbar_set

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awbar_set;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       ignore_bins Ignore_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                   (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awburst_axi3_ace

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awburst_axi3_ace

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst : Crosses cover points coherent_write_xact_type ,burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awdomain

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable & barrier_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awlen_ace

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awlen_ace

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_bresp_all

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_bresp_all

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_barrier_no_writeevict_bresp_no_exclusive

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_cacheinitialstate_cachefinalstate

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_awsnoop_not_ace_lite_barrier_writeevict_cacheinitialstate_cachefinalstate;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     awsnoop_cacheinitialstate_cachefinalstate : cross coherent_write_xact_type, initial_cache_line_state ,
                                                        final_cache_line_state {
              ignore_bins Ignore_writenosnoop_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}));
        ignore_bins Ignore_writeuniqueorline_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins Ignore_writeback_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEBACK}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeevict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (!binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                                ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
         ignore_bins Ignore_writeclean_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins evict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::EVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_invalid_initial_state = ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITENOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY}))|| ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}))||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITECLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN,
                                                       svt_axi_transaction::UNIQUECLEAN})) ||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::EVICT}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::UNIQUEDIRTY,
                                                       svt_axi_transaction::SHAREDDIRTY}));
          ignore_bins Ignore_invalid_xact_types = binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awbar_unset

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awbar_unset

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awbar_unset;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awburst_axi3_ace

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awburst_axi3_ace

This Covergroup captures coherant xact type,burst_type and slave_port_id. It is constructed and sampled when interface_type is not AXI_LITE and cov_trans_cross_slave_port_id_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst : Crosses cover points coherent_write_xact_type , burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awdomain

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awlen_ace

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awlen_ace

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type ,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_all

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_all

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_no_exclusive

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_cacheinitialstate_cachefinalstate

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_no_writeevict_cacheinitialstate_cachefinalstate;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
     final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
    bins final_state_invalid = {svt_axi_transaction::INVALID};
    bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins final_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins final_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
   }
     awsnoop_cacheinitialstate_cachefinalstate : cross coherent_write_xact_type, initial_cache_line_state ,
                                                        final_cache_line_state {
              ignore_bins Ignore_writenosnoop_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}));
        ignore_bins Ignore_writeuniqueorline_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins Ignore_writeback_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEBACK}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeevict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (!binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) ) ||
                                                ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeclean_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins evict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::EVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_invalid_initial_state = ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITENOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY}))|| ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}))||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITECLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN,
                                                       svt_axi_transaction::UNIQUECLEAN})) ||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::EVICT}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::UNIQUEDIRTY,
                                                       svt_axi_transaction::SHAREDDIRTY}));
         ignore_bins Ignore_invalid_xact_types = binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBARRIER};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awbar_unset

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awbar_unset

This Covergroup captures coherant write xact_type and barrier type for write transaction. It is constructed and sampled when trans_cross_ace_awsnoop_awbar_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
barrier_type : Captures write barrier

Cross coverpoints:

awsnoop_awbar : Crosses cover points coherent_write_xact_type and barrier_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awbar_unset;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awbar : cross coherent_write_xact_type, barrier_type {
       ignore_bins Ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awburst_axi3_ace

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awburst_axi3_ace

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_type: Captures transaction burst type

Cross coverpoints:

awsnoop_awburst : Crosses cover points coherent_write_xact_type , burst_type and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awburst_axi3_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awburst : cross coherent_write_xact_type, burst_type , slave_port_id{
       ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) &&
                                                binsof(coherent_write_xact_type) intersect {
                                                svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::EVICT,svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) &&
                                                (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER});
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awdomain

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awdomain

This Covergroup captures coherant write xact_type,domain and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_awdomain_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
domain_type : Captures domain type

Cross coverpoints:

awsnoop_awdomain : Crosses cover points coherent_write_xact_type and domain_type

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awdomain(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_awdomain : cross coherent_write_xact_type, domain_type , slave_port_id{
       ignore_bins Ignore_inner_outer_sharable = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITENOSNOOP}) &&
                                                (binsof(domain_type) intersect {svt_axi_transaction::INNERSHAREABLE,
                                                                                svt_axi_transaction::OUTERSHAREABLE});
       ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                   {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE,
                                                    svt_axi_transaction::EVICT}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_system_sharable = (binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITEEVICT}) &&
                                            (binsof(domain_type) intersect {svt_axi_transaction::SYSTEMSHAREABLE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awlen_ace

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awlen_ace

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
burst_length: Captures transaction burst length

Cross coverpoints:

awsnoop_awlen : Crosses cover points coherent_write_xact_type,burst_length and slave_port_id

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_awlen_ace(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    awsnoop_awlen : cross coherent_write_xact_type, burst_length , slave_port_id{
       ignore_bins Ignore_invalid_length_all = binsof(burst_length) &&
                                                 binsof(coherent_write_xact_type) intersect {
                                                 svt_axi_transaction::WRITELINEUNIQUE,svt_axi_transaction::WRITEBARRIER,
                                                 svt_axi_transaction::EVICT};
       ignore_bins Ignore_non_power_of_2_length = binsof(burst_length) intersect {[2:3],[5:7],[9:15]} &&
                                                 binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEEVICT};
      ignore_bins Ignore_invalid_length_above_16 = binsof(coherent_write_xact_type) intersect {
                                                        svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK} &&
                                                        binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_all

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_all

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_all(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
      ignore_bins Ignore_invalid_bresp = (!binsof(coherent_write_xact_type.coherent_writenosnoop_xact)) &&
                                          binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_no_exclusive

Covergroup:trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_no_exclusive

This Covergroup captures coherant write xact_type , write response and slave_port_id. It is constructed and sampled when trans_cross_ace_awsnoop_bresp_enable & writeevict_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent write transaction
bresp : Captures write response

Cross coverpoints:

awsnoop_bresp : Crosses cover points coherent_write_xact_type and bresp

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_bresp_no_exclusive(int num_slaves);
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     slave_port_id : coverpoint slave_id {
    bins slave_id[] = {[0 : (num_slaves - 1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
     awsnoop_bresp : cross coherent_write_xact_type, bresp, slave_port_id {
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_cacheinitialstate_cachefinalstate

Covergroup: trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_cacheinitialstate_cachefinalstate

Coverpoints:

coherent_write_xact_type : Captures coherent Write transaction
initial_cache_line_state : Captures initial cache line state
final_cache_line_state : Capture final cache line state INVALID,UNIQUECLEAN,SHAREDCLEAN are the possible final states

Cross coverpoints:

awsnoop_cacheinitialstate_cachefinalstate : Crosses cover points coherent_write_xact_type initial_cache_line_state and final_cache_line_state

covergroup trans_cross_ace_awsnoop_not_ace_lite_no_barrier_writeevict_cacheinitialstate_cachefinalstate;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     initial_cache_line_state : coverpoint cov_item.initial_cache_line_state iff (cov_initial_cache_line_state_flag) {
    bins initial_state_invalid = {svt_axi_transaction::INVALID};
    bins initial_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
    bins initial_state_uniquedirty = {svt_axi_transaction::UNIQUEDIRTY};
    bins initial_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
    bins initial_state_shareddirty = {svt_axi_transaction::SHAREDDIRTY};
    option.weight = 0 ;
    type_option.weight = 0 ;
  }
         // For write type transactions such as WRITENOSNOOP, WRITEUNIQUE,
    // WRITELINEUNIQUE, WRITECLEAN, WRITEBACK, EVICT and WRITEEVICT, the possible
    // final states are INVALID, UNIQUECLEAN and SHAREDCLEAN. So Dirty states
    // are not included.
    final_cache_line_state : coverpoint cov_item.final_cache_line_state iff (cov_final_cache_line_state_flag) {
      bins final_state_invalid = {svt_axi_transaction::INVALID};
      bins final_state_uniqueclean = {svt_axi_transaction::UNIQUECLEAN};
      bins final_state_sharedclean = {svt_axi_transaction::SHAREDCLEAN};
      option.weight = 0;
    }
         awsnoop_cacheinitialstate_cachefinalstate : cross coherent_write_xact_type, initial_cache_line_state ,
                                                        final_cache_line_state {
              ignore_bins Ignore_writenosnoop_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITENOSNOOP}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::UNIQUEDIRTY}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}));
        ignore_bins Ignore_writeuniqueorline_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) && (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins Ignore_writeback_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEBACK}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeevict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (!binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) ) ||
                                                ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEEVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_writeclean_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN})) ||
                                               ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITECLEAN}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDDIRTY}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::SHAREDCLEAN}));
        ignore_bins evict_states = ((binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::EVICT}) &&
                                               (binsof(initial_cache_line_state) intersect
                                                    {svt_axi_transaction::UNIQUECLEAN,svt_axi_transaction::SHAREDCLEAN}) &&
                                               (!binsof(final_cache_line_state) intersect
                                                    {svt_axi_transaction::INVALID}));
        ignore_bins Ignore_invalid_initial_state = ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITENOSNOOP}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::SHAREDCLEAN,svt_axi_transaction::SHAREDDIRTY}))|| ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEUNIQUE,svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::UNIQUEDIRTY,svt_axi_transaction::SHAREDDIRTY}))||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBACK,svt_axi_transaction::WRITECLEAN}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::SHAREDCLEAN,
                                                       svt_axi_transaction::UNIQUECLEAN})) ||
                                                     ((binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::EVICT}) &&
                                                      (binsof(initial_cache_line_state) intersect
                                                      {svt_axi_transaction::INVALID,svt_axi_transaction::UNIQUEDIRTY,
                                                       svt_axi_transaction::SHAREDDIRTY}));
         ignore_bins Ignore_invalid_xact_types = binsof(coherent_write_xact_type) intersect
                                                      {svt_axi_transaction::WRITEBARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb39to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_branch_predictor_invalidate = {3'b001};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_va : coverpoint cov_item.addr[0] iff(cov_ardvm_message_flag){
    bins invalidate_by_va = {1'b1};
    bins invalidate_not_by_va = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_branch_predictor_modes_virtaddr_msb39to16 : cross ardvm_message_type, ardvm_va, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb43to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_branch_predictor_invalidate = {3'b001};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_va : coverpoint cov_item.addr[0] iff(cov_ardvm_message_flag){
    bins invalidate_by_va = {1'b1};
    bins invalidate_not_by_va = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_branch_predictor_modes_virtaddr_msb43to16 : cross ardvm_message_type, ardvm_va, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb47to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_branch_predictor_invalidate = {3'b001};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_va : coverpoint cov_item.addr[0] iff(cov_ardvm_message_flag){
    bins invalidate_by_va = {1'b1};
    bins invalidate_not_by_va = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_branch_predictor_modes_virtaddr_msb47to16 : cross ardvm_message_type, ardvm_va, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb55to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_branch_predictor_invalidate = {3'b001};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_va : coverpoint cov_item.addr[0] iff(cov_ardvm_message_flag){
    bins invalidate_by_va = {1'b1};
    bins invalidate_not_by_va = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_branch_predictor_modes_virtaddr_msb55to16 : cross ardvm_message_type, ardvm_va, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Branch Predictor invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_branch_predictor_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_va : Captures ARADDR[0] which implies invalidate by VA or invalidate All
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

dvm_branch_predictor_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_va and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_branch_predictor_invl_modes_virtaddr_msb63to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_branch_predictor_invalidate = {3'b001};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_va : coverpoint cov_item.addr[0] iff(cov_ardvm_message_flag){
    bins invalidate_by_va = {1'b1};
    bins invalidate_not_by_va = {1'b0};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_branch_predictor_modes_virtaddr_msb63to16 : cross ardvm_message_type, ardvm_va, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_addr_range_msb39to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb39to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_addr_range_msb39to16;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_addr_range_msb39to16 : cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_addr_range_msb43to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb43to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_addr_range_msb43to16;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_addr_range_msb43to16 :cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_addr_range_msb47to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb47to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_addr_range_msb47to16;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_addr_range_msb47to16 : cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_addr_range_msb55to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb55to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total Virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_addr_range_msb55to16;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_addr_range_msb55to16 : cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_addr_range_msb63to16

Covergroup: trans_cross_ace_dvm_firstpart_addr_range_msb63to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_addr_range_msb63to16;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_addr_range_msb63to16 :cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_32

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_32

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 32.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_secondpart_32 : Captures SecondPart of DVM of width32

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_32 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_secondpart_32

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_32;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_32 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width32_flag){
    bins dvm_araddr_secondpart_range_1 = {['h0:'h1FFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {['h2000000:'h9FFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {['hA000000:'hFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_32: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_secondpart_32 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_40

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_40

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
araddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and araddr_dvm_secondpart_40

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_40;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_40 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width40_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h1FFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h200000000:64'h9FFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'hA00000000:64'hFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_40: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart, araddr_dvm_secondpart_40 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_44

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_44

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
araddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and araddr_dvm_secondpart_44

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_44;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_44 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width44_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h4000000000:64'h7FFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h8000000000:64'hBFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC000000000:64'hFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_44: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart, araddr_dvm_secondpart_44 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_48

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_48

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
araddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and araddr_dvm_secondpart_48

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_48;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_48 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width48_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h40000000000:64'h7FFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h80000000000:64'hBFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC0000000000:64'hFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_48: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart, araddr_dvm_secondpart_48 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_56

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_56

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
araddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and araddr_dvm_secondpart_56

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_56;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_56 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width56_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h4000000000000:64'h7FFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h8000000000000:64'hBFFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC000000000000:64'hFFFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_56: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart, araddr_dvm_secondpart_56 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_firstpart_secondpart_addr_range_64

Covergroup: trans_cross_ace_dvm_firstpart_secondpart_addr_range_64

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
araddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64

Cross coverpoints:

dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and araddr_dvm_secondpart_64.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_firstpart_secondpart_addr_range_64;
      araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_secondpart_64 : coverpoint dvm_araddr_secondpart_coverpoint iff(cov_dvm_araddr_secondpart_width64_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h400000000000000:64'h7FFFFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h800000000000000:64'hBFFFFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC00000000000000:64'hFFFFFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_firstpart_secondpart_addr_range_64: cross araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart, araddr_dvm_secondpart_64 {
            ignore_bins ignore_bins_dvm_araddr_firstpart_range_3_dvm_araddr_secondpart_range_2 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_3) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_2);
     ignore_bins ignore_bins_dvm_araddr_firstpart_range_3_dvm_araddr_secondpart_range_1 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_3) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_1);
     ignore_bins ignore_bins_dvm_araddr_firstpart_range_2_dvm_araddr_secondpart_range_4 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_2) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_4);
     ignore_bins ignore_bins_dvm_araddr_firstpart_range_1_dvm_araddr_secondpart_range_4 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_1) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_4);
     ignore_bins ignore_bins_dvm_araddr_firstpart_range_1_dvm_araddr_secondpart_range_3 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_1) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_3);
     ignore_bins ignore_bins_dvm_araddr_firstpart_range_1_dvm_araddr_secondpart_range_2 = binsof(araddr_dvm_msb63to32_firstpart.dvm_araddr_firstpart_range_1) && binsof(araddr_dvm_secondpart_64.dvm_araddr_secondpart_range_2);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_phy_inst_cache_invl_bits : coverpoint dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart, dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_phy_inst_cache_invl_bits : coverpoint dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart, dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_phy_inst_cache_invl_bits : coverpoint dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart, dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_phy_inst_cache_invl_bits : coverpoint dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart, dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
dvm_message_phy_inst_cache_invl_bits : Captures types of physical instruction cache invalidation

Cross coverpoints:

dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_phy_inst_cache_invl_bits : coverpoint dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart, dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb39to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_hypervisor_type : coverpoint cov_item.addr[11:10] iff(cov_ardvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_security_type : coverpoint cov_item.addr[9:8] iff(cov_ardvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_addr_mode_bits : coverpoint dvm_addr_mode_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_tlbinvl_modes_virtaddr_msb39to16 : cross ardvm_message_type, ardvm_hypervisor_type, ardvm_security_type, ardvm_addr_mode_bits, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(ardvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(ardvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(ardvm_hypervisor_type) intersect {2'b10}) && (binsof(ardvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb43to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_hypervisor_type : coverpoint cov_item.addr[11:10] iff(cov_ardvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_security_type : coverpoint cov_item.addr[9:8] iff(cov_ardvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_addr_mode_bits : coverpoint dvm_addr_mode_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_tlbinvl_modes_virtaddr_msb43to16 : cross ardvm_message_type, ardvm_hypervisor_type, ardvm_security_type, ardvm_addr_mode_bits, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(ardvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(ardvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(ardvm_hypervisor_type) intersect {2'b10}) && (binsof(ardvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
           option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb47to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_hypervisor_type : coverpoint cov_item.addr[11:10] iff(cov_ardvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_security_type : coverpoint cov_item.addr[9:8] iff(cov_ardvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_addr_mode_bits : coverpoint dvm_addr_mode_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_tlbinvl_modes_virtaddr_msb47to16 : cross ardvm_message_type, ardvm_hypervisor_type, ardvm_security_type, ardvm_addr_mode_bits, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(ardvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(ardvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(ardvm_hypervisor_type) intersect {2'b10}) && (binsof(ardvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb55to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_hypervisor_type : coverpoint cov_item.addr[11:10] iff(cov_ardvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_security_type : coverpoint cov_item.addr[9:8] iff(cov_ardvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_addr_mode_bits : coverpoint dvm_addr_mode_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_tlbinvl_modes_virtaddr_msb55to16 : cross ardvm_message_type, ardvm_hypervisor_type, ardvm_security_type, ardvm_addr_mode_bits, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(ardvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(ardvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(ardvm_hypervisor_type) intersect {2'b10}) && (binsof(ardvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
ardvm_hypervisor_type : Captures OS type
ardvm_security_type : Captures Security type
ardvm_addr_mode_bits : Captures addr invalidate modes
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32

Cross coverpoints:

dvm_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and ardvm_hypervisor_type and ardvm_security_type and ardvm_addr_mode_bits and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_tlbinvl_modes_virtaddr_msb63to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_hypervisor_type : coverpoint cov_item.addr[11:10] iff(cov_ardvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_security_type : coverpoint cov_item.addr[9:8] iff(cov_ardvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     ardvm_addr_mode_bits : coverpoint dvm_addr_mode_bits_coverpoint[5:0] iff(cov_ardvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_tlbinvl_modes_virtaddr_msb63to16 : cross ardvm_message_type, ardvm_hypervisor_type, ardvm_security_type, ardvm_addr_mode_bits, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(ardvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(ardvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(ardvm_hypervisor_type) intersect {2'b10}) && (binsof(ardvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(ardvm_security_type) intersect {2'b11}) && (binsof(ardvm_hypervisor_type) intersect {2'b10}));
          option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb39to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb39to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_virt_inst_cache_invl_bits : coverpoint dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_ardvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
         dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb39to32_firstpart, dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb43to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb43to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_virt_inst_cache_invl_bits : coverpoint dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_ardvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb43to32_firstpart, dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb47to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb47to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_virt_inst_cache_invl_bits : coverpoint dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_ardvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
      dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb47to32_firstpart, dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints ardvm_message_type and and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb55to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb55to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_virt_inst_cache_invl_bits : coverpoint dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_ardvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb55to32_firstpart, dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_port_kind is AXI_MASTER svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

ardvm_message_type : Captures DVM Message Type
araddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
araddr_dvm_firsrpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
araddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
dvm_message_virt_inst_cache_invl_bits : Captures DVM Virtual Instruction Cache invalidate message

Cross coverpoints:

dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints ardvm_message_type and araddr_dvm_firstpart_va_or_vmid and araddr_dvm_firsrpart_va_or_asid and araddr_dvm_msb63to32_firstpart and dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16;
      ardvm_message_type : coverpoint cov_item.addr[14:12] iff(cov_ardvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_firstpart_va_or_vmid : coverpoint dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
   option.weight = 0;
   type_option.weight = 0;
  }
     araddr_dvm_firsrpart_va_or_asid : coverpoint dvm_araddr_firstpart_va_asid_coverpoint iff(cov_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     araddr_dvm_msb63to32_firstpart : coverpoint dvm_araddr_firstpart_msbto32_coverpoint iff(cov_dvm_araddr_firstpart_width32_flag){
    bins dvm_araddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_araddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_message_virt_inst_cache_invl_bits : coverpoint dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_ardvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
    dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16 : cross ardvm_message_type, araddr_dvm_firstpart_va_or_vmid, araddr_dvm_firsrpart_va_or_asid, araddr_dvm_msb63to32_firstpart, dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_readonce_ardomain_arprot

Covergroup: trans_cross_ace_readonce_ardomain_arprot

It is constructed and sampled when trans_cross_ace_readonce_ardomain_arprot_enable is asserted.

Coverpoints:

coherent_read_xact_type: Captures readonce coherent read transaction
domain_type : Captures domain type
prot_type : Captures transaction protection type

Cross coverpoints:

readonce_ardomain_arprot : Crosses cover points coherent_read_xact_type and domain_type and prot_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_ace_readonce_ardomain_arprot;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_READ_XACT_TYPE(`SVT_AXI_COV_WEIGHT_VAL_0)
    coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
      option.weight = 1;
    }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
     readonce_ardomain_arprot : cross coherent_read_xact_type, domain_type, prot_type {
        ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_read_xact_type) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_not_readonce = (!binsof(coherent_read_xact_type) intersect
                                           {svt_axi_transaction::READONCE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[39:32] and ARADDR[31:16]. The total virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb39to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_addr_range_msb39to16;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb39to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_addr_range_msb39to16 :cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb39to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[43:32] and ARADDR[31:16]. The total virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb43to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_addr_range_msb43to16;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb43to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_addr_range_msb43to16 :cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb43to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[47:32] and ARADDR[31:16]. The total virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb47to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_addr_range_msb47to16;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb47to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_addr_range_msb47to16 :cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb47to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[55:32] and ARADDR[31:16]. The total virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb55to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_addr_range_msb55to16;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb55to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_addr_range_msb55to16 :cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb55to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16

This covergroup is cross coverage of FirstPart of DVM (Virtual Address) on ARADDR[63:32] and ARADDR[31:16]. The total virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32

Cross coverpoints:

snoop_dvm_firstpart_addr_range_msb63to16 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_addr_range_msb63to16;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb63to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width32_flag){
    bins dvm_acaddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_acaddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_acaddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_addr_range_msb63to16 :cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb63to32_firstpart {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[39:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[39:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
acaddr_dvm_secondpart_40 : Captures SecondPart of DVM of width40

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_40 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and acaddr_dvm_secondpart_40

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_40;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb39to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_secondpart_40 : coverpoint snoop_dvm_araddr_secondpart_coverpoint iff(cov_snoop_dvm_araddr_secondpart_width40_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h1FFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h200000000:64'h9FFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'hA00000000:64'hFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_secondpart_addr_range_40: cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb39to32_firstpart, acaddr_dvm_secondpart_40 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[43:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[43:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
acaddr_dvm_secondpart_44 : Captures SecondPart of DVM of width44

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_44 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and acaddr_dvm_secondpart_44

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_44;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb43to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_secondpart_44 : coverpoint snoop_dvm_araddr_secondpart_coverpoint iff(cov_snoop_dvm_araddr_secondpart_width44_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h4000000000:64'h7FFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h8000000000:64'hBFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC000000000:64'hFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_secondpart_addr_range_44: cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb43to32_firstpart, acaddr_dvm_secondpart_44 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[47:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[47:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
acaddr_dvm_secondpart_48 : Captures SecondPart of DVM of width48

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_48 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and acaddr_dvm_secondpart_48

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_48;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb47to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_secondpart_48 : coverpoint snoop_dvm_araddr_secondpart_coverpoint iff(cov_snoop_dvm_araddr_secondpart_width48_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h40000000000:64'h7FFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h80000000000:64'hBFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC0000000000:64'hFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_secondpart_addr_range_48: cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb47to32_firstpart, acaddr_dvm_secondpart_48 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[55:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[55:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
acaddr_dvm_secondpart_56 : Captures SecondPart of DVM of width56

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_56 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and acaddr_dvm_secondpart_56

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_56;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb55to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_secondpart_56 : coverpoint snoop_dvm_araddr_secondpart_coverpoint iff(cov_snoop_dvm_araddr_secondpart_width56_flag){
    bins dvm_araddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_2 = {[64'h4000000000000:64'h7FFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_3 = {[64'h8000000000000:64'hBFFFFFFFFFFFF]};
    bins dvm_araddr_secondpart_range_4 = {[64'hC000000000000:64'hFFFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_secondpart_addr_range_56: cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb55to32_firstpart, acaddr_dvm_secondpart_56 {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64

Covergroup: trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64

This covergroup is cross coverage of snoop FirstPart of DVM (Virtual Address) on ARADDR[63:32], ARADDR[31:16] and SecondPart of DVM on ARADDR[63:4]. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_firstpart_secondpart_addr_range_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
acaddr_dvm_secondpart_64 : Captures SecondPart of DVM of width64

Cross coverpoints:

snoop_dvm_firstpart_secondpart_addr_range_64 : Crosses coverpoints acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and acaddr_dvm_secondpart_64

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_firstpart_secondpart_addr_range_64;
      acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb63to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width32_flag){
    bins dvm_acaddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_acaddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_acaddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_secondpart_64 : coverpoint snoop_dvm_araddr_secondpart_coverpoint iff(cov_snoop_dvm_araddr_secondpart_width64_flag){
    bins dvm_acaddr_secondpart_range_1 = {[64'h0:64'h3FFFFFFFFFFFFFF]};
    bins dvm_acaddr_secondpart_range_2 = {[64'h400000000000000:64'h7FFFFFFFFFFFFFF]};
    bins dvm_acaddr_secondpart_range_3 = {[64'h800000000000000:64'hBFFFFFFFFFFFFFF]};
    bins dvm_acaddr_secondpart_range_4 = {[64'hC00000000000000:64'hFFFFFFFFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         snoop_dvm_firstpart_secondpart_addr_range_64: cross acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb63to32_firstpart, acaddr_dvm_secondpart_64 {
            ignore_bins ignore_bins_dvm_acaddr_firstpart_range_3_dvm_acaddr_secondpart_range_2 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_3) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_2);
     ignore_bins ignore_bins_dvm_acaddr_firstpart_range_3_dvm_acaddr_secondpart_range_1 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_3) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_1);
     ignore_bins ignore_bins_dvm_acaddr_firstpart_range_2_dvm_acaddr_secondpart_range_4 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_2) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_4);
     ignore_bins ignore_bins_dvm_acaddr_firstpart_range_1_dvm_acaddr_secondpart_range_4 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_1) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_4);
     ignore_bins ignore_bins_dvm_acaddr_firstpart_range_1_dvm_acaddr_secondpart_range_3 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_1) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_3);
     ignore_bins ignore_bins_dvm_acaddr_firstpart_range_1_dvm_acaddr_secondpart_range_2 = binsof(acaddr_dvm_msb63to32_firstpart.dvm_acaddr_firstpart_range_1) && binsof(acaddr_dvm_secondpart_64.dvm_acaddr_secondpart_range_2);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb39to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb39to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_phy_inst_cache_invl_bits : coverpoint snoop_dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb39to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb39to32_firstpart, snoop_dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb43to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb43to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_phy_inst_cache_invl_bits : coverpoint snoop_dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb43to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb43to32_firstpart, snoop_dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb47to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb47to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_phy_inst_cache_invl_bits : coverpoint snoop_dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb47to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb47to32_firstpart, snoop_dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb55to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb55to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_phy_inst_cache_invl_bits : coverpoint snoop_dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb55to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb55to32_firstpart, snoop_dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM Physical Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_phy_inst_cache_invl_modes_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
snoop_dvm_message_phy_inst_cache_invl_bits : Captures physical instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_phy_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_phy_inst_cache_invl_modes_virtaddr_msb63to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_physical_instruction_cache_invalidate = {3'b010};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb63to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width32_flag){
    bins dvm_acaddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_acaddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_acaddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_phy_inst_cache_invl_bits : coverpoint snoop_dvm_message_phy_inst_cache_invl_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
     bins invl_by_pa_with_virt_index_sec_phy_inst_cache ={6 'b100111};
   bins invl_by_pa_with_virt_index_non_sec_phy_inst_cache ={6 'b110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_phy_inst_cache_invl_modes_virtaddr_msb63to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb63to32_firstpart, snoop_dvm_message_phy_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16

This covergroup is cross coverage ofsnoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb39to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_hypervisor_type : coverpoint cov_snoop_item.snoop_addr[11:10] iff(cov_acdvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_security_type : coverpoint cov_snoop_item.snoop_addr[9:8] iff(cov_acdvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_addr_mode_bits : coverpoint snoop_dvm_addr_mode_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb39to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_snoop_tlbinvl_modes_virtaddr_msb39to16 : cross acdvm_message_type, acdvm_hypervisor_type, acdvm_security_type, acdvm_addr_mode_bits, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb39to32_firstpart {
       ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(acdvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(acdvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(acdvm_hypervisor_type) intersect {2'b10}) && (binsof(acdvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width12

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb43to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_hypervisor_type : coverpoint cov_snoop_item.snoop_addr[11:10] iff(cov_acdvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_security_type : coverpoint cov_snoop_item.snoop_addr[9:8] iff(cov_acdvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_addr_mode_bits : coverpoint snoop_dvm_addr_mode_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb43to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_snoop_tlbinvl_modes_virtaddr_msb43to16 : cross acdvm_message_type, acdvm_hypervisor_type, acdvm_security_type, acdvm_addr_mode_bits, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb43to32_firstpart {
       ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(acdvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(acdvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(acdvm_hypervisor_type) intersect {2'b10}) && (binsof(acdvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb47to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_hypervisor_type : coverpoint cov_snoop_item.snoop_addr[11:10] iff(cov_acdvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_security_type : coverpoint cov_snoop_item.snoop_addr[9:8] iff(cov_acdvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_addr_mode_bits : coverpoint snoop_dvm_addr_mode_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb47to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
         dvm_snoop_tlbinvl_modes_virtaddr_msb47to16 : cross acdvm_message_type, acdvm_hypervisor_type, acdvm_security_type, acdvm_addr_mode_bits, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb47to32_firstpart {
      ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(acdvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(acdvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(acdvm_hypervisor_type) intersect {2'b10}) && (binsof(acdvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb55to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_hypervisor_type : coverpoint cov_snoop_item.snoop_addr[11:10] iff(cov_acdvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_security_type : coverpoint cov_snoop_item.snoop_addr[9:8] iff(cov_acdvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_addr_mode_bits : coverpoint snoop_dvm_addr_mode_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb55to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_snoop_tlbinvl_modes_virtaddr_msb55to16 : cross acdvm_message_type, acdvm_hypervisor_type, acdvm_security_type, acdvm_addr_mode_bits, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb55to32_firstpart {
       ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(acdvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(acdvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(acdvm_hypervisor_type) intersect {2'b10}) && (binsof(acdvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM TLB Invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_tlbinvl_modes_virtaddr_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acdvm_hypervisor_type : Captures OS type
acdvm_security_type : Captures Security type
acdvm_addr_mode_bits : Captures addr invalidate modes
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM Virtual address MSB to 32 of width32

Cross coverpoints:

dvm_snoop_tlbinvl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acdvm_hypervisor_type and acdvm_security_type and acdvm_addr_mode_bits and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_tlbinvl_modes_virtaddr_msb63to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_tlb_invalidate = {3'b000};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_hypervisor_type : coverpoint cov_snoop_item.snoop_addr[11:10] iff(cov_acdvm_message_flag){
    bins all_guest_os = {2'b10};
    bins hypervisor_and_all_guest_os = {2'b00};
    bins hypervisor = {2'b11};
    bins el = {2'b01};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_security_type : coverpoint cov_snoop_item.snoop_addr[9:8] iff(cov_acdvm_message_flag){
    bins no_secure = {2'b11};
    bins secure = {2'b10};
    bins secure_and_no_secure = {2'b00};
    option.weight = 0;
    type_option.weight = 0;
  }
     acdvm_addr_mode_bits : coverpoint snoop_dvm_addr_mode_bits_coverpoint[5:0] iff(cov_acdvm_message_flag){
      bins invl_all_guestOS_stage1_invl_only= {6'b100010};
    bins invl_all_guestOS_stage1_stage2 = {6'b100000};
    bins invl_by_va_guestOS = {6'b100001};
    bins invl_by_va_guestOS_leaf_entry_only= {6'b101001};
    bins invl_by_asid_guestOS = {6'b110000};
    bins invl_by_asid_va_guestOS = {6'b110001};
    bins invl_by_asid_va_guestOS_leaf_entry_only = {6'b111001};
    bins invl_by_ipa_guestOS = {6'b100101};
    bins invl_by_ipa_guestOS_leaf_entry_only = {6'b101101};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb63to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width32_flag){
    bins dvm_acaddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_acaddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_acaddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     dvm_snoop_tlbinvl_modes_virtaddr_msb63to16 : cross acdvm_message_type, acdvm_hypervisor_type, acdvm_security_type, acdvm_addr_mode_bits, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb63to32_firstpart {
       ignore_bins ignore_bins_hypervisor_and_all_guest_os = (binsof(acdvm_hypervisor_type) intersect {2'b00});
    ignore_bins ignore_bins_hypervisor = (binsof(acdvm_hypervisor_type) intersect {2'b00,2'b11,2'b01});
  ignore_bins ignore_bins_guest_os_and_secure_and_non_secure = ((binsof(acdvm_hypervisor_type) intersect {2'b10}) && (binsof(acdvm_security_type) intersect {2'b00,2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) &&
                                                                                (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_and_va_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
  ignore_bins ignore_bins_no_secure_and_invl_by_asid_va_leaf_entry_only_hypervisor_all_guest_os = ((binsof(acdvm_security_type) intersect {2'b11}) && (binsof(acdvm_hypervisor_type) intersect {2'b10}));
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 24 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 40.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb39to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width8
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16 : Crosses coverpoints acdvm_message_typ and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb39to32_firstpar and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb39to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb39to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width8_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3F]};
    bins dvm_araddr_firstpart_range_2 = {['h40:'h7F]};
    bins dvm_araddr_firstpart_range_3 = {['h80:'hBF]};
    bins dvm_araddr_firstpart_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_virt_inst_cache_invl_bits : coverpoint snoop_dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_acdvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb39to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb39to32_firstpart, snoop_dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 28 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 44.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb43to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width12
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb43to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb43to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb43to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width12_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h3FF]};
    bins dvm_araddr_firstpart_range_2 = {['h400:'h7FF]};
    bins dvm_araddr_firstpart_range_3 = {['h800:'hBFF]};
    bins dvm_araddr_firstpart_range_4 = {['hC00:'hFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_virt_inst_cache_invl_bits : coverpoint snoop_dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_acdvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb43to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb43to32_firstpart, snoop_dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 32 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 48.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb47to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width16
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb47to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb47to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb47to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width16_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'h1FFF]};
    bins dvm_araddr_firstpart_range_2 = {['h2000:'h9FFF]};
    bins dvm_araddr_firstpart_range_3 = {['hA000:'hFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_virt_inst_cache_invl_bits : coverpoint snoop_dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_acdvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb47to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb47to32_firstpart, snoop_dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 40 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 56.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb55to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width24
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb55to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb55to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb55to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width24_flag){
    bins dvm_araddr_firstpart_range_1 = {['h0:'hFFFFF]};
    bins dvm_araddr_firstpart_range_2 = {['h100000:'h6FFFFF]};
    bins dvm_araddr_firstpart_range_3 = {['h700000:'hBFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_virt_inst_cache_invl_bits : coverpoint snoop_dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_acdvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb55to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb55to32_firstpart, snoop_dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

Covergroup: trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16

This covergroup is cross coverage of snoop DVM Virtual Instruction Cache invalidate message type, invalidate address modes and virtual address range. The virtual address width is 48 bits. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_configuration :: trans_cross_ace_dvm_virt_inst_cache_invl_modes_cov_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: cov_snoop_addr_6_bit_flag = 1 svt_axi_port_configuration :: addr_width = 64.

Coverpoints:

acdvm_message_type : Captures DVM Message Type
acaddr_dvm_firstpart_va_or_vmid : Captures firstpart of DVM Virtual address or VMID
acaddr_dvm_firstpart_va_or_asid : Captures firstpart of DVM Virtual address or ASID
acaddr_dvm_msb63to32_firstpart : Captures firstpart of DVM VA MSB to 32 of width32
snoop_dvm_message_virt_inst_cache_invl_bits : Captures virtual instruction cache invalidate by pa etc

Cross coverpoints:

dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16 : Crosses coverpoints acdvm_message_type and acaddr_dvm_firstpart_va_or_vmid and acaddr_dvm_firstpart_va_or_asid and acaddr_dvm_msb63to32_firstpart and snoop_dvm_message_virt_inst_cache_invl_bits

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_cross_ace_snoop_dvm_virt_inst_cache_invl_modes_virtaddr_msb63to16;
      acdvm_message_type : coverpoint cov_snoop_item.snoop_addr[14:12] iff(cov_acdvm_message_flag){
    bins message_virtual_instruction_cache_invalidate = {3'b011};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_vmid : coverpoint snoop_dvm_araddr_firstpart_va_vmid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_vmid_flag){
    bins dvm_araddr_bits_31to24_range_1 = {['h0:'h3F]};
    bins dvm_araddr_bits_31to24_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_31to24_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_31to24_range_4 = {['hC0:'hFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_firstpart_va_or_asid : coverpoint snoop_dvm_araddr_firstpart_va_asid_coverpoint iff(cov_snoop_dvm_araddr_viraddr_or_asid_flag){
    bins dvm_araddr_bits_23to16_range_1 = {['h0:'h3F]};
      bins dvm_araddr_bits_23to16_range_2 = {['h40:'h7F]};
    bins dvm_araddr_bits_23to16_range_3 = {['h80:'hBF]};
    bins dvm_araddr_bits_23to16_range_4 = {['hC0:'hFF]};
      option.weight = 0;
    type_option.weight = 0;
  }
     acaddr_dvm_msb63to32_firstpart : coverpoint snoop_dvm_araddr_firstpart_msbto32_coverpoint iff(cov_snoop_dvm_araddr_firstpart_width32_flag){
    bins dvm_acaddr_firstpart_range_1 = {[64'h0:64'hFFFFFFF]};
    bins dvm_acaddr_firstpart_range_2 = {[64'h10000000:64'h8FFFFFFF]};
    bins dvm_acaddr_firstpart_range_3 = {[64'h90000000:64'hFFFFFFFF]};
    option.weight = 0;
    type_option.weight = 0;
  }
     snoop_dvm_message_virt_inst_cache_invl_bits : coverpoint snoop_dvm_message_virt_inst_cache_invl_bits_coverpoint[7:0] iff(cov_acdvm_message_flag){
     bins invl_all_non_sec_guest_os ={8'b10110100};
   bins invl_by_asid_and_va_non_sec_guest_os ={8'b10110111};
     option.weight = 0;
   type_option.weight = 0;
}
     dvm_snoop_virt_inst_cache_invl_modes_virtaddr_msb63to16 : cross acdvm_message_type, acaddr_dvm_firstpart_va_or_vmid, acaddr_dvm_firstpart_va_or_asid, acaddr_dvm_msb63to32_firstpart, snoop_dvm_message_virt_inst_cache_invl_bits {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_ace_writeunique_awdomain_awprot

Covergroup: trans_cross_ace_writeunique_awdomain_awprot

It is constructed and sampled when trans_cross_ace_writeunique_awdomain_awprot_enable is asserted

Coverpoints:

coherent_write_xact_type: Captures writeunique coherent write transaction
domain_type : Captures domain type
prot_type : Captures transaction protection type

Cross coverpoints:

writeunique_awdomain_awprot : Crosses cover points coherent_write_xact_type and domain_type and prot_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_ace_writeunique_awdomain_awprot;
     //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_WRITE_XACT_TYPE
    coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
      option.weight = 1;
    }
     domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
    bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
    bins domain_inner_shareable = {svt_axi_transaction::INNERSHAREABLE};
    bins domain_outer_shareable = {svt_axi_transaction::OUTERSHAREABLE};
    bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
     writeunique_awdomain_awprot : cross coherent_write_xact_type, domain_type, prot_type {
        ignore_bins Ignore_non_and_system_sharable = (binsof(coherent_write_xact_type) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE}) &&
                                                   (binsof(domain_type) intersect {svt_axi_transaction::NONSHAREABLE,
                                                                                   svt_axi_transaction::SYSTEMSHAREABLE});
       ignore_bins Ignore_not_write_unique = (!binsof(coherent_write_xact_type) intersect
                                           {svt_axi_transaction::WRITEUNIQUE});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_comp_awburst_awsize

This covergroup captures attributes for compare operation,burst_size and burst_type for Atomic transaction. Covergroup: trans_cross_atomic_comp_awburst_awsize

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

comp_xact_type: Captures atomic compare transaction
comp_op_type: Captures atomic compare operation type
burst_type: Captures burst_type
burst_size: Captures burst_size

Cross coverpoints:

atomic_comp_awburst_awsize: Crosses cover points comp_xact_type,comp_op_type, burst_type and burst_size

covergroup trans_cross_atomic_comp_awburst_awsize;
      atomic_comp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_comp_xact_type_flag){
   bins atomic_compare_xact = {svt_axi_transaction::COMPARE};
   option.weight = 0 ;
   type_option.weight = 0;
  }
     atomic_comp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_comp_op_type_flag){
    bins atomic_compare = {svt_axi_transaction::ATOMICCOMPARE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_burst_type : coverpoint cov_item.burst_type iff(cov_atomic_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
  option.weight = 0;
  type_option.weight = 0;
  }
     atomic_comp_burst_size : coverpoint cov_item.burst_size iff(cov_atomic_comp_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
  option.weight = 0;
  type_option.weight = 0;
  }
     atomic_comp_awburst_awsize : cross atomic_comp_xact_type, atomic_comp_op_type,atomic_burst_type,atomic_comp_burst_size{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_comp_bresp_burst_length

This covergroup captures attributes for compare operation,burst_size and burst_type for Atomic transaction. Covergroup: trans_cross_atomic_comp_bresp_burt_length

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

comp_xact_type: Captures atomic compare transaction
comp_op_type: Captures atomic compare operation type
burst_length: Captures burst_length
atomic_bresp: Captures response for no exclusive

Cross coverpoints:

atomic_comp_type_bresp_burst_length: Crosses cover points comp_xact_type,comp_op_type, bresp and burst_length

covergroup trans_cross_atomic_comp_bresp_burst_length;
      atomic_comp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_comp_xact_type_flag){
   bins atomic_compare_xact = {svt_axi_transaction::COMPARE};
   option.weight = 0 ;
   type_option.weight = 0;
  }
     atomic_comp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_comp_op_type_flag){
    bins atomic_compare = {svt_axi_transaction::ATOMICCOMPARE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]}iff(cfg.axi_interface_type == svt_axi_port_configuration::AXI4);
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    atomic_comp_type_bresp_burst_length : cross atomic_comp_xact_type, atomic_comp_op_type, bresp ,burst_length{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_comp_endianness

This covergroup captures attributes for compare transaction type, operation and endian type for Atomic transaction. Covergroup: trans_cross_atomic_comp_endianness

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

comp_xact_type: Captures atomic compare transaction
comp_op_type: Captures compare operation type
endian_type: Captures endianness for atomic compare transaction

Cross coverpoints:

atomic_comp_endian: Crosses cover points comp_xact_type,comp_op_type and endian_type

covergroup trans_cross_atomic_comp_endianness;
      atomic_comp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_comp_xact_type_flag){
   bins atomic_compare_xact = {svt_axi_transaction::COMPARE};
   option.weight = 0 ;
   type_option.weight = 0;
  }
     atomic_comp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_comp_op_type_flag){
    bins atomic_compare = {svt_axi_transaction::ATOMICCOMPARE};
    option.weight = 0;
    type_option.weight = 0;
  }
     endian_type : coverpoint cov_item.endian iff(cov_endian_flag){
   bins little_endian = {svt_axi_transaction::LITTLE_ENDIAN};
   bins big_endian = {svt_axi_transaction::BIG_ENDIAN};
   option.weight = 0;
   type_option.weight = 0;
}
    atomic_comp_endian : cross atomic_comp_xact_type,atomic_comp_op_type,endian_type{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_comp_rresp_burst_length

This covergroup captures attributes for compare transaction type, operation ,burst_length and response check for Atomic transaction. Covergroup: trans_cross_atomic_comp_burst_length

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

comp_xact_type: Captures atomic compare transaction
comp_op_type: Captures atomic compare operation type
burst_length: Captures burst_length
atomic_rresp: Captures response for no exclusive

Cross coverpoints:

atomic_comp_type_rresp_burst_length: Crosses cover points comp_xact_type,comp_op_type,rresp and burst_length

covergroup trans_cross_atomic_comp_rresp_burst_length;
      atomic_comp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_comp_xact_type_flag){
   bins atomic_compare_xact = {svt_axi_transaction::COMPARE};
   option.weight = 0 ;
   type_option.weight = 0;
  }
     atomic_comp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_comp_op_type_flag){
    bins atomic_compare = {svt_axi_transaction::ATOMICCOMPARE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]}iff(cfg.axi_interface_type == svt_axi_port_configuration::AXI4);
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_comp_rresp_burst_length : cross atomic_comp_xact_type, atomic_comp_op_type, rresp ,burst_length{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_noncomp_awburst_awsize

This covergroup captures attributes for atomic compare operation,burst_size and burst_type for Atomic transaction. Covergroup: trans_cross_atomic_noncomp_awburst_awsize

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

noncomp_xact_type: Captures atomic transaction for noncomp
noncomp_op_type: Captures atomic compare operation type
burst_type: Captures burst_type
noncomp_burst_size: Captures burst_size

Cross coverpoints:

atomic_noncomp_awburst_awsize: Crosses cover points comp_xact_type,comp_op_type, burst_type and burst_size

covergroup trans_cross_atomic_noncomp_awburst_awsize;
      atomic_burst_type : coverpoint cov_item.burst_type iff(cov_atomic_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
  option.weight = 0;
  type_option.weight = 0;
  }
     atomic_noncomp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_noncomp_xact_type_flag){
    bins atomic_swap_xact = {svt_axi_transaction::SWAP};
    bins atomic_load_xact = {svt_axi_transaction::LOAD};
    bins atomic_store_xact = {svt_axi_transaction::STORE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_noncomp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_noncomp_op_type_flag){
    bins atomic_store_add = {svt_axi_transaction::ATOMICSTORE_ADD };
    bins atomic_store_clr = {svt_axi_transaction::ATOMICSTORE_CLR };
    bins atomic_store_eor = {svt_axi_transaction::ATOMICSTORE_EOR };
    bins atomic_store_set = {svt_axi_transaction::ATOMICSTORE_SET };
    bins atomic_store_smax = {svt_axi_transaction::ATOMICSTORE_SMAX };
    bins atomic_store_smin = {svt_axi_transaction::ATOMICSTORE_SMIN };
    bins atomic_store_umax = {svt_axi_transaction::ATOMICSTORE_UMAX };
    bins atomic_store_umin = {svt_axi_transaction::ATOMICSTORE_UMIN };
    bins atomic_load_add = {svt_axi_transaction::ATOMICLOAD_ADD };
    bins atomic_load_clr = {svt_axi_transaction::ATOMICLOAD_CLR };
    bins atomic_load_eor = {svt_axi_transaction::ATOMICLOAD_EOR };
    bins atomic_load_set = {svt_axi_transaction::ATOMICLOAD_SET };
    bins atomic_load_smax = {svt_axi_transaction::ATOMICLOAD_SMAX };
    bins atomic_load_smin = {svt_axi_transaction::ATOMICLOAD_SMIN };
    bins atomic_load_umax = {svt_axi_transaction::ATOMICLOAD_UMAX };
    bins atomic_load_umin = {svt_axi_transaction::ATOMICLOAD_UMIN };
    bins atomic_swap = {svt_axi_transaction::ATOMICSWAP };
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_non_comp_burst_size : coverpoint cov_item.burst_size iff(cov_atomic_non_comp_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    atomic_noncomp_awburst_awsize : cross atomic_noncomp_xact_type, atomic_noncomp_op_type,atomic_burst_type,atomic_non_comp_burst_size{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_noncomp_bresp_burst_length

This covergroup captures attributes for noncompare operation,burst_size and burst_type for Atomic transaction. Covergroup: trans_cross_atomic_noncomp_awburst_awsize

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

noncomp_xact_type: Captures atomic noncompare transaction
noncomp_op_type: Captures atomic noncompare operation type
burst_length: Captures burst_length
atomic_bresp: Captures response for no exclusive

Cross coverpoints:

atomic_noncomp_type_bresp_burst_length: Crosses cover points noncomp_xact_type,noncomp_op_type,bresp and burst_length

covergroup trans_cross_atomic_noncomp_bresp_burst_length;
      atomic_noncomp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_noncomp_xact_type_flag){
    bins atomic_swap_xact = {svt_axi_transaction::SWAP};
    bins atomic_load_xact = {svt_axi_transaction::LOAD};
    bins atomic_store_xact = {svt_axi_transaction::STORE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]}iff(cfg.axi_interface_type == svt_axi_port_configuration::AXI4);
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_noncomp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_noncomp_op_type_flag){
    bins atomic_store_add = {svt_axi_transaction::ATOMICSTORE_ADD };
    bins atomic_store_clr = {svt_axi_transaction::ATOMICSTORE_CLR };
    bins atomic_store_eor = {svt_axi_transaction::ATOMICSTORE_EOR };
    bins atomic_store_set = {svt_axi_transaction::ATOMICSTORE_SET };
    bins atomic_store_smax = {svt_axi_transaction::ATOMICSTORE_SMAX };
    bins atomic_store_smin = {svt_axi_transaction::ATOMICSTORE_SMIN };
    bins atomic_store_umax = {svt_axi_transaction::ATOMICSTORE_UMAX };
    bins atomic_store_umin = {svt_axi_transaction::ATOMICSTORE_UMIN };
    bins atomic_load_add = {svt_axi_transaction::ATOMICLOAD_ADD };
    bins atomic_load_clr = {svt_axi_transaction::ATOMICLOAD_CLR };
    bins atomic_load_eor = {svt_axi_transaction::ATOMICLOAD_EOR };
    bins atomic_load_set = {svt_axi_transaction::ATOMICLOAD_SET };
    bins atomic_load_smax = {svt_axi_transaction::ATOMICLOAD_SMAX };
    bins atomic_load_smin = {svt_axi_transaction::ATOMICLOAD_SMIN };
    bins atomic_load_umax = {svt_axi_transaction::ATOMICLOAD_UMAX };
    bins atomic_load_umin = {svt_axi_transaction::ATOMICLOAD_UMIN };
    bins atomic_swap = {svt_axi_transaction::ATOMICSWAP };
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_noncomp_type_bresp_burst_length : cross atomic_noncomp_xact_type, atomic_noncomp_op_type, bresp ,burst_length{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_noncomp_endianness

This covergroup captures attributes for noncompare transaction type, operation and endian type for Atomic transaction. Covergroup: trans_cross_atomic_noncomp_endianness

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

noncomp_xact_type: Captures atomic noncompare transaction
noncomp_op_type: Captures noncompare operation type
endian_type: Captures endianness for atomic noncompare transaction

Cross coverpoints:

atomic_noncomp_endian: Crosses cover points noncomp_xact_type,noncomp_op_type and endian_type

covergroup trans_cross_atomic_noncomp_endianness;
      atomic_noncomp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_noncomp_xact_type_flag){
    bins atomic_swap_xact = {svt_axi_transaction::SWAP};
    bins atomic_load_xact = {svt_axi_transaction::LOAD};
    bins atomic_store_xact = {svt_axi_transaction::STORE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_noncomp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_noncomp_op_type_flag){
    bins atomic_store_add = {svt_axi_transaction::ATOMICSTORE_ADD };
    bins atomic_store_clr = {svt_axi_transaction::ATOMICSTORE_CLR };
    bins atomic_store_eor = {svt_axi_transaction::ATOMICSTORE_EOR };
    bins atomic_store_set = {svt_axi_transaction::ATOMICSTORE_SET };
    bins atomic_store_smax = {svt_axi_transaction::ATOMICSTORE_SMAX };
    bins atomic_store_smin = {svt_axi_transaction::ATOMICSTORE_SMIN };
    bins atomic_store_umax = {svt_axi_transaction::ATOMICSTORE_UMAX };
    bins atomic_store_umin = {svt_axi_transaction::ATOMICSTORE_UMIN };
    bins atomic_load_add = {svt_axi_transaction::ATOMICLOAD_ADD };
    bins atomic_load_clr = {svt_axi_transaction::ATOMICLOAD_CLR };
    bins atomic_load_eor = {svt_axi_transaction::ATOMICLOAD_EOR };
    bins atomic_load_set = {svt_axi_transaction::ATOMICLOAD_SET };
    bins atomic_load_smax = {svt_axi_transaction::ATOMICLOAD_SMAX };
    bins atomic_load_smin = {svt_axi_transaction::ATOMICLOAD_SMIN };
    bins atomic_load_umax = {svt_axi_transaction::ATOMICLOAD_UMAX };
    bins atomic_load_umin = {svt_axi_transaction::ATOMICLOAD_UMIN };
    bins atomic_swap = {svt_axi_transaction::ATOMICSWAP };
    option.weight = 0;
    type_option.weight = 0;
  }
     endian_type : coverpoint cov_item.endian iff(cov_endian_flag){
   bins little_endian = {svt_axi_transaction::LITTLE_ENDIAN};
   bins big_endian = {svt_axi_transaction::BIG_ENDIAN};
   option.weight = 0;
   type_option.weight = 0;
}
    atomic_noncomp_endian : cross atomic_noncomp_xact_type,atomic_noncomp_op_type,endian_type{
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_atomic_noncomp_rresp_burst_length

This covergroup captures attributes for noncompare transaction type, operation ,burst_length and response check for Atomic transaction. Covergroup: trans_cross_atomic_noncomp_rresp_burst_length

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

noncomp_xact_type: Captures atomic compare transaction
burst_length: Captures burst_length
atomic_rresp: Captures response for no exclusive
noncomp_op_type: Captures noncomp,operation type

Cross coverpoints:

atomic_noncomp_type_rresp_burst_length: Crosses cover points noncomp_xact_type,noncomp_op_type, rresp and burst_length

covergroup trans_cross_atomic_noncomp_rresp_burst_length;
      atomic_noncomp_xact_type : coverpoint cov_item.atomic_transaction_type iff(cov_atomic_noncomp_xact_type_flag){
    bins atomic_swap_xact = {svt_axi_transaction::SWAP};
    bins atomic_load_xact = {svt_axi_transaction::LOAD};
    bins atomic_store_xact = {svt_axi_transaction::STORE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]}iff(cfg.axi_interface_type == svt_axi_port_configuration::AXI4);
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_noncomp_op_type : coverpoint cov_item.atomic_xact_op_type iff(cov_atomic_noncomp_op_type_flag){
    bins atomic_store_add = {svt_axi_transaction::ATOMICSTORE_ADD };
    bins atomic_store_clr = {svt_axi_transaction::ATOMICSTORE_CLR };
    bins atomic_store_eor = {svt_axi_transaction::ATOMICSTORE_EOR };
    bins atomic_store_set = {svt_axi_transaction::ATOMICSTORE_SET };
    bins atomic_store_smax = {svt_axi_transaction::ATOMICSTORE_SMAX };
    bins atomic_store_smin = {svt_axi_transaction::ATOMICSTORE_SMIN };
    bins atomic_store_umax = {svt_axi_transaction::ATOMICSTORE_UMAX };
    bins atomic_store_umin = {svt_axi_transaction::ATOMICSTORE_UMIN };
    bins atomic_load_add = {svt_axi_transaction::ATOMICLOAD_ADD };
    bins atomic_load_clr = {svt_axi_transaction::ATOMICLOAD_CLR };
    bins atomic_load_eor = {svt_axi_transaction::ATOMICLOAD_EOR };
    bins atomic_load_set = {svt_axi_transaction::ATOMICLOAD_SET };
    bins atomic_load_smax = {svt_axi_transaction::ATOMICLOAD_SMAX };
    bins atomic_load_smin = {svt_axi_transaction::ATOMICLOAD_SMIN };
    bins atomic_load_umax = {svt_axi_transaction::ATOMICLOAD_UMAX };
    bins atomic_load_umin = {svt_axi_transaction::ATOMICLOAD_UMIN };
    bins atomic_swap = {svt_axi_transaction::ATOMICSWAP };
    option.weight = 0;
    type_option.weight = 0;
  }
    atomic_noncomp_rresp_burst_length : cross atomic_noncomp_xact_type, atomic_noncomp_op_type, rresp ,burst_length{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_awunique_awsnoop_awbar_without_barrier

Covergroup: trans_cross_awunique_awsnoop_awbar_without_barrier

This Covergroup captures coherant write xact_type,awunique_val,barrier_type and awunique_awsnoop_awbar values for write transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_READ_ONLY and barrier_enable set to 0.

Coverpoints:

coherent_write_xact_type: Captures write transction type. Includes WRITENOSNOOP, WRITEUNIQUE, WRITELINEUNIQUE, WRITECLEAN, WRITEBACK, EVICT, WRITEBARRIER and WRITEEVICT
awunique_val: Captures the value of signal AWUNIQUE in above transactions
barrier_type: Captures the value of barrier type (AWBAR), in above transactions
awunique_awsnoop_awbar: Cross of coherent_write_xact_type, awunique_val and barrier_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4

covergroup trans_cross_awunique_awsnoop_awbar_without_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    ignore_bins ignore_barrier = {svt_axi_transaction::MEMORY_BARRIER,
                                       svt_axi_transaction::SYNC_BARRIER} iff(cfg.barrier_enable == 1'b0);
    option.weight = 0;
    type_option.weight = 0;
  }
    awunique_val: coverpoint cov_item.is_unique {
      bins is_not_unique = {0};
      bins is_unique = {1};
      option.weight = 0;
    }
    awunique_awsnoop_awbar : cross coherent_write_xact_type, awunique_val, barrier_type {
      ignore_bins ignore_writeevict = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEEVICT} && binsof(awunique_val) intersect {0};
      ignore_bins ignore_writeclean = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITECLEAN} && binsof(awunique_val) intersect {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_awunique_awsnoop_awbar_with_barrier

Covergroup: trans_cross_awunique_awsnoop_awbar_with_barrier

Coverpoints:

coherent_write_xact_type: Captures write transction type. Includes WRITENOSNOOP, WRITEUNIQUE, WRITELINEUNIQUE, WRITECLEAN, WRITEBACK, EVICT, WRITEBARRIER and WRITEEVICT
awunique_val: Captures the value of signal AWUNIQUE in above transactions
barrier_type: Captures the value of barrier type (AWBAR), in above transactions

Cross Coverpoints:

awunique_awsnoop_awbar: Cross of coherent_write_xact_type, awunique_val and barrier_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4

covergroup trans_cross_awunique_awsnoop_awbar_with_barrier;
      coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    option.weight = 0;
    type_option.weight = 0;
  }
     barrier_type : coverpoint cov_item.barrier_type iff(cov_barrier_type_flag){
    bins barrier_normal_respect = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER};
    bins barrier_memory = {svt_axi_transaction::MEMORY_BARRIER};
    bins barrier_normal_ignore = {svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
    bins barrier_synchronization = {svt_axi_transaction::SYNC_BARRIER};
    ignore_bins ignore_barrier = {svt_axi_transaction::MEMORY_BARRIER,
                                       svt_axi_transaction::SYNC_BARRIER} iff(cfg.barrier_enable == 1'b0);
    option.weight = 0;
    type_option.weight = 0;
  }
    awunique_val: coverpoint cov_item.is_unique {
      bins is_not_unique = {0};
      bins is_unique = {1};
      option.weight = 0;
    }
     awunique_awsnoop_awbar : cross coherent_write_xact_type, awunique_val, barrier_type {
      ignore_bins ignore_writeevict = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEEVICT} && binsof(awunique_val) intersect {0};
      ignore_bins ignore_writeclean = binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITECLEAN} && binsof(awunique_val) intersect {1};
      // Ignore NORMAL_ACCESS_RESPECT_BARRIER and NORMAL_ACCESS_IGNORE_BARRIER for barrier transaction
      ignore_bins ignore_normal = (binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,
                                                                   svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER});
      // Ignore MEMORY_BARRIER and SYNC_BARRIER for non-barrier transaction
      ignore_bins ignore_barrier = (!binsof(coherent_write_xact_type) intersect {svt_axi_transaction::WRITEBARRIER}) &&
                                  (binsof(barrier_type) intersect {svt_axi_transaction::MEMORY_BARRIER,
                                                                   svt_axi_transaction::SYNC_BARRIER});
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_ace

Covergroup: trans_cross_axi_arburst_arlen_ace

This covergroup captures attributes of burst_type & burst_length for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

covergroup trans_cross_axi_arburst_arlen_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen : cross read_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dweq_1024bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range when data width is 1024 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_1024bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 1024 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_128bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 128 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_16bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_256bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 256 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_32bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 32 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_512bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 512 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_64bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 64 for read transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_ace_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dweq_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_16bit

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range for data width less than 16 for read transaction. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_256bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_512bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi3_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dweq_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_16bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_256bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_512bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_min_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_32bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_32bit

Coverpoints:

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range when data width is 32 for read transaction. It is constructed and sampled when interface_type is AXI4_LITE.

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_64bit

Covergroup: trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_64bit

Coverpoints:

This covergroup captures attributes of read_burst_type,burst_length ,burst_size and address range when data width is 64 for read transaction. It is constructed and sampled when interface_type is AXI4_LITE.

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_arburst_arlen_araddr_arsize_axi4_lite_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_araddr_arsize : cross read_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_axi3

Covergroup: trans_cross_axi_arburst_arlen_araddr_axi3

This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_arburst_arlen_araddr_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_arburst_arlen_araddr_min : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_araddr_axi4

Covergroup: trans_cross_axi_arburst_arlen_araddr_axi4

This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_arburst_arlen_araddr_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_arburst_arlen_araddr_min : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_arburst_arlen_araddr_mid : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_arburst_arlen_araddr_max : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arcache_ace

Covergroup: trans_cross_axi_arburst_arlen_arcache_ace

This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_arburst_arlen_arcache_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arcache : cross read_xact_type, burst_type, burst_length, cache_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arcache_axi3

Covergroup: trans_cross_axi_arburst_arlen_arcache_axi3

This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_arburst_arlen_arcache_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins non_cacheable_non_bufferable = {0};
    bins bufferable_or_modifiable_only = {1};
    bins cacheable_but_no_alloc = {2};
    bins cacheable_bufferable_but_no_alloc = {3};
    bins cacheable_write_through_allocate_on_read_only = {6};
    bins cacheable_write_back_allocate_on_read_only = {7};
    bins cacheable_write_through_allocate_on_write_only = {10};
    bins cacheable_write_back_allocate_on_write_only = {11};
    bins cacheable_write_through_allocate_on_both_read_write = {14};
    bins cacheable_write_back_allocate_on_both_read_write = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arcache : cross read_xact_type, burst_type, burst_length, cache_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arcache_axi4

Covergroup: trans_cross_axi_arburst_arlen_arcache_axi4

This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when interface type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_arburst_arlen_arcache_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arcache : cross read_xact_type, burst_type, burst_length, cache_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arcache_axi4_lite

Covergroup: trans_cross_axi_arburst_arlen_arcache_axi4_lite

This covergroup captures attributes of burst_type,burst_length and cache_type for read transaction. It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_arburst_arlen_arcache: Crosses cover points read_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_arburst_arlen_arcache_axi4_lite;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arcache : cross read_xact_type, burst_type, burst_length, cache_type{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arprot_ace

Covergroup: trans_cross_axi_arburst_arlen_arprot_ace

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_arburst_arlen_arprot_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arprot : cross read_xact_type, burst_type, burst_length, prot_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arprot_axi3

Covergroup: trans_cross_axi4_arburst_arlen_arprot

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_arburst_arlen_arprot_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arprot : cross read_xact_type, burst_type, burst_length, prot_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arprot_axi4

Covergroup: trans_cross_axi_arburst_arlen_arprot_axi4

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_arburst_arlen_arprot_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arprot : cross read_xact_type, burst_type, burst_length, prot_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arprot_axi4_lite

Covergroup: trans_cross_axi_arburst_arlen_arprot_axi4_lite

This covergroup captures attributes of burst_type,burst_length and protection signal for read transaction. It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_arburst_arlen_arprot: Crosses cover points read_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_arburst_arlen_arprot_axi4_lite;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arprot : cross read_xact_type, burst_type, burst_length, prot_type{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dweq_1024bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is 1024 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_1024bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 1024 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_128bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 128 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_16bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 16 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_256bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 256 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_32bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 32 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_512bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 512 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_ace_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_ace_dwlt_64bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is less than 64 bit. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_ace_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dweq_128bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is 1024 bit. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_16bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_256bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_512bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi3_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dweq_1024bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is 1024 bit. It is constructed and sampled when interface_type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_16bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_256bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_512bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dweq_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dweq_1024bit

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction when data width is 1024 bit. It is constructed and sampled when interface_type is AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dweq_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_1024bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_1024bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_1024bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif SVT_AXI_MON_CFG_BASED_COV_GRP_DEF
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_128bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_16bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_16bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_16bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_256bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_256bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_32bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_512bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_512bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_64bit

Covergroup: trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_arsize: Crosses cover points read_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_arburst_arlen_arsize_axi4_lite_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arsize : cross read_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_axi3

Covergroup: trans_cross_axi_arburst_arlen_axi3

This covergroup captures attributes of burst_type & burst_length for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

covergroup trans_cross_axi_arburst_arlen_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen : cross read_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_axi4

Covergroup: trans_cross_axi_arburst_arlen_axi4

This covergroup captures attributes of burst_type & burst_length for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

covergroup trans_cross_axi_arburst_arlen_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen : cross read_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_axi4_lite

Covergroup: trans_cross_axi_arburst_arlen_axi4_lite

This covergroup captures attributes of burst_type & burst_length for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_arburst_arlen: Crosses cover points read_xact_type, burst_type and burst_length

covergroup trans_cross_axi_arburst_arlen_axi4_lite;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen : cross read_xact_type, burst_type, burst_length {
    //`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
    // ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
    //`endif
    // ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_rresp_all_axi3

Covergroup: trans_cross_axi_arburst_arlen_rresp_all_axi3

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI3 or AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_arlen_rresp_all_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arlen_rresp_all_axi4

Covergroup: trans_cross_axi_arburst_arlen_rresp_all_axi4

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_arlen_rresp_all_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(rresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arqos_ace

This covergroup captures attributes of burst_type and qos for A transaction at subordinate. Covergroup: trans_cross_axi_arburst_arqos_ace

It is constructed when interface type can be AXI_ACE or ACE_LITE It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_arburst_arqos_ace: Crosses cover points read_xact_type, burst_type and qos

covergroup trans_cross_axi_arburst_arqos_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     qos : coverpoint cov_item.qos iff(cov_qos_type_flag){
    bins qos_range_0_1 = {[0:1]};
    bins qos_range_2_3 = {[2:3]};
    bins qos_range_4_7 = {[4:7]};
    bins qos_range_8_15 = {[8:15]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arqos : cross read_xact_type, burst_type, qos {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_arqos_axi4

This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_arburst_arqos_axi4

It is constructed when interface type can be AXI4. It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_arburst_arqos: Crosses cover points read_xact_type, burst_type and qos

covergroup trans_cross_axi_arburst_arqos_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     qos : coverpoint cov_item.qos iff(cov_qos_type_flag){
    bins qos_range_0_1 = {[0:1]};
    bins qos_range_2_3 = {[2:3]};
    bins qos_range_4_7 = {[4:7]};
    bins qos_range_8_15 = {[8:15]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arqos : cross read_xact_type, burst_type, qos {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi3_ace_arlen_ace_araddr_ace

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_ace_araddr_ace

This covergroup captures attributes of burst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_arburst_axi3_ace_arlen_ace_araddr_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    axi_arburst_arlen_araddr : cross read_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_exclusive_not_axi3

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_exclusive_not_axi3

This covergroup captures attributes of burst_type,burst_length and atomic_type for read normal & exclusive transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE & exclusive_access_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_exclusive_not_axi3;
       read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_no_exclusive_not_axi3

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_no_exclusive_not_axi3

This covergroup captures attributes of burst_type,burst_length and atomic_type for read normal transaction. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE .

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_arburst_axi3_ace_arlen_ace_arlock_no_exclusive_not_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_all

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_all

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_all;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(rresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_no_exclusive

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_no_exclusive

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_axi3_ace_arlen_ace_rresp_no_exclusive;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_araddr_axi3_axi4

Covergroup: trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_araddr_axi3_axi4

This covergroup captures attributes of read_xburst_type & burst_length & address range for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_arburst_arlen_araddr: Crosses cover points read_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_araddr_axi3_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_arburst_arlen_araddr : cross read_xact_type, burst_type, burst_length, addr {
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_arlock_exclusive_not_axi3

Covergroup: trans_cross_axi_arburst_axi3_ace_arlen_axi4_lite_arlock_exclusive_not_axi3

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_arlock_exclusive_not_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_arlock_no_exclusive_not_axi3

Covergroup: trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_arlock_no_exclusive_not_axi3

This covergroup captures attributes of burst_type,burst_length and atomic_type for read normal transaction. It is constructed and sampled when interface_type is AXI4_LITE .

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_arlock_no_exclusive_not_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_all

Covergroup: trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_all

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when trans_cross_axi_arburst_arlen_rresp_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_all;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(rresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_no_exclusive

Covergroup: trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_no_exclusive

This covergroup captures attributes of read_burst_type & burst_length & response type for read transaction at subordinate. It is constructed and sampled when interface type is set to AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
rresp: Captures transaction response

Cross coverpoints:

axi_arburst_arlen_rresp: Crosses cover points read_xact_type, burst_type, burst_length, rresp

covergroup trans_cross_axi_arburst_axi4_lite_arlen_axi4_lite_rresp_no_exclusive;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_rresp : cross read_xact_type, burst_type, burst_length, rresp{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_128bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_128bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 128. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data_width is 128.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_128bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_128bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_32bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_32bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 32. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data_width is 32.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_32bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_32bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_64bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_64bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 64. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data_width is 64.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_64bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_ace_dweq_64bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_128bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_128bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 128. It is constructed and sampled when interface type is AXI3 and data_width is 128.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_128bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_128bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_32bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_32bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 32. It is constructed and sampled when interface type is AXI3 and data_width is 32.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_32bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_32bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_64bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_64bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 64. It is constructed and sampled when interface type is AXI3 and data_width is 64.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_64bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi3_dweq_64bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_128bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_128bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 128. It is constructed and sampled when interface type is AXI4 and data_width is 128.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_128bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_128bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_32bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_32bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 32. It is constructed and sampled when interface type is AXI4 and data_width is 32.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_32bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_32bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_64bit

Covergroup: trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_64bit

This cover group crosses bit ARCACHE[1] with unaligned read transfers for data_width 64. It is constructed and sampled when interface type is AXI4 and data_width is 64.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures ARCACHE[1]

Cross coverpoints:

axi_read_arcache_modifiable_bit_unaligned_transfer_dweq_64bit: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arcache_modifiable_bit_read_unaligned_transfer_axi4_dweq_64bit : cross read_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_bresp_all_axi3

Covergroup: trans_cross_axi_atomictype_bresp_all_axi3

This covergroup is triggered when a Write transaction with locked access is observed. It is constructed and sampled when interface type is AXI3 & locked_access_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

covergroup trans_cross_axi_atomictype_bresp_all_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_bresp : cross write_xact_type, atomic_type,bresp{
        ignore_bins Ignore_invalid_atomic_exokay_resp = !binsof(atomic_type.exclusive) && binsof(bresp.exokay_resp);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_bresp_all_axi4

Covergroup: trans_cross_axi_atomictype_bresp_all_axi4

This covergroup is triggered when a Write transaction with exclusive access is observed. It is constructed and sampled when interface type is AXI3,AXI4 OR AXI4_LITE & exclusive_access_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

covergroup trans_cross_axi_atomictype_bresp_all_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_bresp : cross write_xact_type, atomic_type,bresp{
        ignore_bins Ignore_locked = binsof(atomic_type.locked);
        ignore_bins Ignore_invalid_atomic_exokay_resp = !binsof(atomic_type.exclusive) && binsof(bresp.exokay_resp);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_bresp_all_axi4lite

Covergroup: trans_cross_axi_atomictype_bresp_all_axi4lite

It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

covergroup trans_cross_axi_atomictype_bresp_all_axi4lite;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_bresp : cross write_xact_type, atomic_type,bresp{
       ignore_bins Ignore_not_normal = !binsof(atomic_type.normal);
       ignore_bins Ignore_exokay_resp = binsof(bresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_bresp_exclusive_ace

Covergroup: trans_cross_axi_atomictype_bresp_exclusive_ace

This covergroup is triggered when a Write transaction with exclusive access is observed. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

covergroup trans_cross_axi_atomictype_bresp_exclusive_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_bresp : cross write_xact_type, atomic_type,bresp{
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_bresp_normal_ace

Covergroup: trans_cross_axi_atomictype_bresp_normal_ace

This covergroup is triggered when a Write transaction with exclusive access is observed. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
bresp: Captures transaction response

Cross coverpoints:
axi_atomictype_bresp: Crosses cover points write_xact_type, atomic_type,bresp.

covergroup trans_cross_axi_atomictype_bresp_normal_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_bresp : cross write_xact_type, atomic_type,bresp{
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_exclusive_arcache_exclusive_ace

Covergroup: trans_cross_axi_atomictype_arcache_exclusive_ace

This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values for exclusive access. The legal ARCACHE values for read exclusive access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

covergroup trans_cross_axi_atomictype_exclusive_arcache_exclusive_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_exclusive_arcache : cross read_xact_type, atomic_type,cache_type{
    option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_exclusive_arcache_normal_ace

Covergroup: trans_cross_axi_atomictype_exclusive_arcache_normal_ace

This covergroup is cross coverage of READ Exclusive Access with all legel ARCache values for normal access. The legal ARCACHE values for read normal access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

covergroup trans_cross_axi_atomictype_exclusive_arcache_normal_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_exclusive_arcache : cross read_xact_type, atomic_type,cache_type{
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_exclusive_awcache_exclusive_ace

Covergroup: trans_cross_axi_atomictype_exclusive_awcache_exclusive_ace

This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE OR ACE_LITE and exclusibve_access_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

covergroup trans_cross_axi_atomictype_exclusive_awcache_exclusive_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_exclusive_awcache : cross write_xact_type, atomic_type,cache_type{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_exclusive_awcache_normal_ace

Covergroup: trans_cross_axi_atomictype_exclusive_awcache_normal_ace

This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for normal access. The legal AWCACHE values for normal write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI_ACE OR ACE_LITE and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

covergroup trans_cross_axi_atomictype_exclusive_awcache_normal_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_exclusive_awcache : cross write_xact_type, atomic_type,cache_type{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_rresp_all_axi3

Covergroup: trans_cross_axi_atomictype_rresp_all_axi3

This covergroup is It is constructed and sampled when interface type is AXI3 and locked_access_enable is asserted. Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp.

covergroup trans_cross_axi_atomictype_rresp_all_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_rresp : cross read_xact_type, atomic_type,rresp{
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_rresp_all_axi4

Covergroup: trans_cross_axi_atomictype_rresp_all_axi4

This covergroup captures attributes of read response and lock signal for read transaction. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp.

covergroup trans_cross_axi_atomictype_rresp_all_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_rresp : cross read_xact_type, atomic_type,rresp{
      ignore_bins Ignore_locked = binsof(atomic_type.locked);
      ignore_bins Ignore_invalid_atomic_exokay_resp = !binsof(atomic_type.exclusive) && binsof(rresp.exokay_resp);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_rresp_all_axi4lite

Covergroup: trans_cross_axi_atomictype_rresp_all_axi4lite

It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp.

covergroup trans_cross_axi_atomictype_rresp_all_axi4lite;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_rresp : cross read_xact_type, atomic_type,rresp{
        ignore_bins Ignore_not_normal = !binsof(atomic_type.normal);
        ignore_bins Ignore_exokay = binsof(rresp.exokay_resp);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_rresp_exclusive_ace

Covergroup: trans_cross_axi_atomictype_rresp_normal_ace

This covergroup is triggered when a READ transaction with exclusive access is observed. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE & exclusive_access_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp.

covergroup trans_cross_axi_atomictype_rresp_exclusive_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_rresp : cross read_xact_type, atomic_type,rresp{
          option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_atomictype_rresp_normal_ace

Covergroup: trans_cross_axi_atomictype_rresp_normal_ace

This covergroup is triggered when a READ transaction with normal access is observed. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
rresp: Captures transaction response

Cross coverpoints:

axi_atomictype_rresp: Crosses cover points read_xact_type, atomic_type,rresp.

covergroup trans_cross_axi_atomictype_rresp_normal_ace;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
     rresp : coverpoint cov_rresp iff(cov_rresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_rresp : cross read_xact_type, atomic_type,rresp{
         option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_ace

This covergroup captures attributes of transaction type,burst_type & burst_length for write transaction It is constructed and sampled when interface type is set to AXI_ACE or ACE_LITE.

Covergroup: trans_cross_axi_awburst_awlen_ace

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

covergroup trans_cross_axi_awburst_awlen_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen : cross write_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dweq_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dweq_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is 1024 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 1024 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_128bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_128bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 128 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_16bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_16bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 16 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_256bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_256bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 256 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_32bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_16bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 32 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_512bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_512bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 512 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_64bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_ace_dwlt_64bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 64 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_ace_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dweq_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dweq_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is 1024 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 1024 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_128bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_128bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 128 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_16bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_16bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 16 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_256bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_256bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 256 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_32bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_32bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 32 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_512bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_512bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 512 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_64bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi3_dwlt_64bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width less than 64 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi3_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dweq_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dweq_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is 1024 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_1024bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_1024bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 1024 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_128bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_128bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 128 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_16bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_16bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 16 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_256bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_256bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 256 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_32bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_32bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 32 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_512bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_512bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 512 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_64bit

Covergroup: trans_cross_axi4_awburst_awlen_awaddr_awsize_axi4_dwlt_64bit

This covergroup describes about burst_type,burst_length ,address and size signal for write transfer and data width is less than 64 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi4_awburst_awlen_awaddr_awsize: Crosses cover points write_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_min_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1} ;
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_32bit

Covergroup: trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_32bit

Coverpoints:

This covergroup captures attributes of burst_type,burst_length ,burst_size and address range when data width is 32 for write transaction. It is constructed and sampled when interface_type is AXI4_LITE.

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_64bit

Covergroup: trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_64bit

Coverpoints:

This covergroup captures attributes of burst_type,burst_length ,burst_size and address range when data width is 64 for write transaction. It is constructed and sampled when interface_type is AXI4_LITE.

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address
burst_size: Captures transaction burst size

Cross coverpoints:

axi_arburst_arlen_araddr_arsize: Crosses cover points read_xact_type, burst_type, burst_length, addr, burst_size

covergroup trans_cross_axi_awburst_awlen_awaddr_awsize_axi4_lite_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awaddr_awsize : cross write_xact_type, burst_type, burst_length, addr, burst_size {
      ignore_bins Ignore_invalid_max_addr_incr_burst_length = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_incr_burst_size = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_size) intersect { 0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_axi3

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI3.

Covergroup: trans_cross_axi_awburst_awlen_awaddr_axi3

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_awburst_awlen_awaddr_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_awburst_awlen_awaddr_min : cross write_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid : cross write_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max : cross write_xact_type, burst_type, burst_length, addr{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awaddr_axi4

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI4.

Covergroup: trans_cross_axi_awburst_awlen_awaddr_axi4

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_awburst_awlen_awaddr_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_awburst_awlen_awaddr_min : cross write_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_mid_max_addr = !binsof(addr.addr_range_min);
      type_option.weight = 1;
      option.weight = 1;
    }
     axi_awburst_awlen_awaddr_mid : cross write_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_min_max_addr = !binsof(addr.addr_range_mid);
      type_option.weight = 100;
      option.weight = 100;
    }
     axi_awburst_awlen_awaddr_max : cross write_xact_type, burst_type, burst_length, addr{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      ignore_bins Ignore_min_mid_addr = !binsof(addr.addr_range_max);
      type_option.weight = 1;
      option.weight = 1;
    }
    option.per_instance = 1;
     endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awcache_ace

Covergroup: trans_cross_axi_awburst_awlen_awcache_ace

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_awburst_awlen_awcache_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awcache : cross write_xact_type, burst_type, burst_length, cache_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awcache_axi3

Covergroup: trans_cross_axi_awburst_awlen_awcache_axi3

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_awburst_awlen_awcache_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins non_cacheable_non_bufferable = {0};
    bins bufferable_or_modifiable_only = {1};
    bins cacheable_but_no_alloc = {2};
    bins cacheable_bufferable_but_no_alloc = {3};
    bins cacheable_write_through_allocate_on_read_only = {6};
    bins cacheable_write_back_allocate_on_read_only = {7};
    bins cacheable_write_through_allocate_on_write_only = {10};
    bins cacheable_write_back_allocate_on_write_only = {11};
    bins cacheable_write_through_allocate_on_both_read_write = {14};
    bins cacheable_write_back_allocate_on_both_read_write = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awcache : cross write_xact_type, burst_type, burst_length, cache_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awcache_axi4

Covergroup: trans_cross_axi_awburst_awlen_awcache_axi3

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_awburst_awlen_awcache_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awcache : cross write_xact_type, burst_type, burst_length, cache_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awcache_axi4_lite

Covergroup: trans_cross_axi_awburst_awlen_awcache_axi4_lite

This covergroup describes about burst_type,burst_length and cache signal for write transfer. It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
cache_type: Captures transaction cache type

Cross coverpoints:

axi_awburst_awlen_awcache: Crosses cover points write_xact_type, burst_type, burst_length, cache_type

covergroup trans_cross_axi_awburst_awlen_awcache_axi4_lite;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awcache : cross write_xact_type, burst_type, burst_length, cache_type {
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awprot_ace

Covergroup: trans_cross_axi_awburst_awlen_awprot_ace

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_awburst_awlen_awprot_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awprot : cross write_xact_type, burst_type, burst_length, prot_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awprot_axi3

Covergroup: trans_cross_axi_awburst_awlen_awprot_axi3

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_awburst_awlen_awprot_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awprot : cross write_xact_type, burst_type, burst_length, prot_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awprot_axi4

Covergroup: trans_cross_axi_awburst_awlen_awprot_axi4

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_awburst_awlen_awprot_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awprot : cross write_xact_type, burst_type, burst_length, prot_type {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awprot_axi4_lite

Covergroup: trans_cross_axi_awburst_awlen_awprot_axi4_lite

This covergroup describes about burst_type,burst_length and protection signal for write transfer. It is constructed when interface type is AXI4_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
prot_type: Captures transaction protection type

Cross coverpoints:

axi_awburst_awlen_awprot: Crosses cover points write_xact_type, burst_type, burst_length, prot_type

covergroup trans_cross_axi_awburst_awlen_awprot_axi4_lite;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     prot_type : coverpoint cov_item.prot_type iff(cov_prot_type_flag){
    bins data_secure_normal = {svt_axi_transaction::DATA_SECURE_NORMAL};
    bins data_secure_privileged = {svt_axi_transaction::DATA_SECURE_PRIVILEGED};
    bins data_non_secure_normal = {svt_axi_transaction::DATA_NON_SECURE_NORMAL};
    bins data_non_secure_privileged = {svt_axi_transaction::DATA_NON_SECURE_PRIVILEGED};
    bins instruction_secure_normal = {svt_axi_transaction::INSTRUCTION_SECURE_NORMAL};
    bins instruction_secure_privileged = {svt_axi_transaction::INSTRUCTION_SECURE_PRIVILEGED};
    bins instruction_non_secure_normal = {svt_axi_transaction::INSTRUCTION_NON_SECURE_NORMAL};
    bins instruction_non_secure_privileged = {svt_axi_transaction::INSTRUCTION_NON_SECURE_PRIVILEGED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awprot : cross write_xact_type, burst_type, burst_length, prot_type {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dweq_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dweq_512bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is 1024 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is 1024 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dweq_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_512bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 1024 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 1024 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_128bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_128bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 128 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 128bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_128bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_16bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_16bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 16 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 16bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_16bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_256bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_256bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 256 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 256bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_256bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_32bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_32bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 32 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 32bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_32bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_512bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_512bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 512 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 512bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_512bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_ace_dwlt_64bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_ace_dwlt_64bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than 64 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and data width is less than 64bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

ace_awburst_awlen_awsize_dwlt_64bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_ace_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dweq_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_1024bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is 1024 bit. It is constructed and sampled when interface type is AXI3 and data width is 1024 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dweq_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_1024bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_128bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_128bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_128bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_16bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_16bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_16bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_256bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_256bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_256bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_32bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_32bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_32bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_512bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_512bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_512bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_64bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_64bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_64bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi3_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dweq_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dweq_1024bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is 1024 bit. It is constructed and sampled when interface type is AXI4 and data width is 1024 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dweq_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_1024bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_128bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_128bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_128bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_16bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_16bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_16bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_256bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_256bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_256bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_32bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_32bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_32bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_512bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_512bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_256bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_64bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_64bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_32bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dweq_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dweq_1024bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is 1024 bit. It is constructed and sampled when interface type is AXI4_LITE and data width is 1024 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dweq_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dweq_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_1024bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_1024bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_1024bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_1024bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_128bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_128bit

This covergroup describes for burst_type,burst_length and burst_size for write transfer when data width is less than128 bit. It is constructed and sampled when interface type is AXI4_LITE and data width is less than 128 bits.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_128bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_16bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_16bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_16bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_16bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_256bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_256bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_256bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_32bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_32bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_32bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_512bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_512bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_512bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_64bit

Covergroup: trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_64bit

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
burst_size: Captures transaction burst size

Cross coverpoints:

axi_awburst_awlen_awsize_dwlt_64bit: Crosses cover points write_xact_type, burst_type, burst_length, burst_size

covergroup trans_cross_axi_awburst_awlen_awsize_axi4_lite_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awsize : cross write_xact_type, burst_type, burst_length, burst_size{
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_axi3

This covergroup captures attributes of transaction type,burst_type & burst_length for write transaction It is constructed and sampled when interface type is set to AXI3.

Covergroup: trans_cross_axi_awburst_awlen_axi3

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

covergroup trans_cross_axi_awburst_awlen_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     axi_awburst_awlen : cross write_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_axi4

This covergroup captures attributes of transaction type,burst_type & burst_length for write transaction It is constructed and sampled when interface type is set to AXI4.

Covergroup: trans_cross_axi_awburst_awlen_axi4

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

covergroup trans_cross_axi_awburst_awlen_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen : cross write_xact_type, burst_type, burst_length {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_axi4_lite

This covergroup captures attributes of transaction type,burst_type & burst_length for write transaction It is constructed and sampled when interface type is set to AXI4_LITE.

Covergroup: trans_cross_axi_awburst_awlen_axi4_lite

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length

Cross coverpoints:

axi_awburst_awlen: Crosses cover points write_xact_type, burst_type and burst_length

covergroup trans_cross_axi_awburst_awlen_axi4_lite;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen : cross write_xact_type, burst_type, burst_length {
//`ifndef SVT_AXI_MAX_BURST_LENGTH_WIDTH_1
// ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect {`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
//`endif
// ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[`SVT_AXI_FIXED_IGNORE_MIN_VALUE:`SVT_AXI_FIXED_IGNORE_MAX_VALUE]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_bresp_all_axi3

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction It is constructed and sampled when interface type is set to AXI3.

Covergroup: trans_cross_axi_awburst_bresp_all_axi3

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_awlen_bresp_all_axi3;
       write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(bresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awlen_bresp_all_axi4

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI4 .

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_axi4_bresp_all

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response for all

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_awlen_bresp_all_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(bresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awqos_ace

This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_awburst_awqos_ace

It is constructed when interface type can be AXI_ACE or ACE-LITE. It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos

covergroup trans_cross_axi_awburst_awqos_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     qos : coverpoint cov_item.qos iff(cov_qos_type_flag){
    bins qos_range_0_1 = {[0:1]};
    bins qos_range_2_3 = {[2:3]};
    bins qos_range_4_7 = {[4:7]};
    bins qos_range_8_15 = {[8:15]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awqos : cross write_xact_type, burst_type, qos {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_awqos_axi4

This covergroup captures attributes of burst_type and qos for AXI transaction at subordinate. Covergroup: trans_cross_axi_awburst_awqos_axi4

It is constructed when interface type can be AXI4. It is sampled when transaction type is set to WRITE OR READ_WRITE

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
qos: Captures ranges of QOS values

Cross coverpoints:

axi_awburst_awqos: Crosses cover points write_xact_type, burst_type and qos

covergroup trans_cross_axi_awburst_awqos_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     qos : coverpoint cov_item.qos iff(cov_qos_type_flag){
    bins qos_range_0_1 = {[0:1]};
    bins qos_range_2_3 = {[2:3]};
    bins qos_range_4_7 = {[4:7]};
    bins qos_range_8_15 = {[8:15]};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awqos : cross write_xact_type, burst_type, qos {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi3_ace_awlen_ace_awaddr_ace

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI4.

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_ace_awaddr_ace

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_awburst_axi3_ace_awlen_ace_awaddr_ace;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
     ignore_bins Ignore_addr_range_max = {((64'd2**(cfg_addr_width))-1)} ;
     ignore_bins Ignore_addr_range_min = {0} ;
  }
    axi_awburst_awlen_awaddr : cross write_xact_type, burst_type, burst_length, addr {
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      ignore_bins Ignore_invalid_max_addr_wrap_burst = binsof(addr.addr_range_max) && binsof(burst_type.wrap_burst);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_exclusive_not_axi3

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_exclusive_not_axi3

This covergroup describes about burst_type,burst_length and lock signal for normal and exclusive write transfer. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE and exclusive_access_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_exclusive_not_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_no_exclusive_not_axi3

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_no_exclusive_not_axi3

This covergroup describes about burst_type,burst_length and lock signal for normal write transfer. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_awburst_axi3_ace_awlen_ace_awlock_no_exclusive_not_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_all

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI4 .

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_all

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response for no exclusive

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_all;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(bresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_no_exclusive

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI4 .

Covergroup: trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_no_exclusive

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response for no exclusive

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_axi3_ace_awlen_ace_bresp_no_exclusive;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_ace = {[256+1:((1<<10))]};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awaddr_axi3_axi4

This covergroup captures attributes of transaction type,burst_type & burst_length and addr range for write transaction It is constructed and sampled when interface type is set to AXI4_LITE.

Covergroup: trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awaddr_axi3_axi4

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
addr: Captures min, mid and max range of transaction address

Cross coverpoints:

axi_awburst_awlen_awaddr: Crosses cover points write_xact_type, burst_type, burst_length, addr

covergroup trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awaddr_axi3_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr : coverpoint cov_item.addr iff(cov_addr_flag){
    option.weight = 0;
    type_option.weight = 0;
     bins addr_range_min = {0} ;
     bins addr_range_mid = {[1:(64'd2**(cfg_addr_width)-2)]};
     bins addr_range_max = {((64'd2**(cfg_addr_width))-1)};
  }
    axi_awburst_awlen_awaddr : cross write_xact_type, burst_type, burst_length, addr {
       ignore_bins Ignore_invalid_max_addr_incr_burst = binsof(addr.addr_range_max) && binsof(burst_type.incr_burst) && !binsof(burst_length) intersect {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_exclusive_not_axi3

Covergroup: trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_exclusive_not_axi3

This covergroup describes about burst_type,burst_length and lock signal for exclusive normal write transfer. It is constructed and sampled when interface type is AXI4_LITE & exclusive_access_enable is asserted.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_exclusive_not_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      option.weight = 1;
    }
    option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_no_exclusive_not_axi3

Covergroup: trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_no_exclusive_not_axi3

This covergroup describes about burst_type,burst_length and lock signal for normal write transfer. It is constructed and sampled when interface type is AXI4_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_awlock_no_exclusive_not_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      option.weight = 1;
    }
    option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_all

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI4_LITE

Covergroup: trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_all

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response for no exclusive

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_all;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins exokay_resp = {svt_axi_transaction::EXOKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      ignore_bins Ignore_invalid_excl_burst = binsof(bresp.exokay_resp) && !binsof(burst_length) intersect {1, 2,4,8,16};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_no_exclusive

This covergroup captures attributes of transaction type,burst_type & burst_length and response for write transaction. It is constructed and sampled when interface type is set to AXI4_LITE

Covergroup: trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_no_exclusive

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
bresp: Captures transaction response for no exclusive

Cross coverpoints:

axi_awburst_awlen_bresp: Crosses cover points write_xact_type, burst_type, burst_length, bresp

covergroup trans_cross_axi_awburst_axi4_lite_awlen_axi4_lite_bresp_no_exclusive;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins incr_burst = {svt_axi_transaction::INCR};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
     bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
    bins okay_resp = {svt_axi_transaction::OKAY};
    bins slverr_resp = {svt_axi_transaction::SLVERR};
    bins decerr_resp = {svt_axi_transaction::DECERR};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_bresp : cross write_xact_type, burst_type, burst_length, bresp{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_128bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_128bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 128. It is constructed and sampled when interface type is AXI_ACE or AC_LITE and data_width is 128.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_128bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_32bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_32bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 32. It is constructed and sampled when interface type is AXI_ACE or AC_LITE and data_width is 32.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_32bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_64bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_64bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 64. It is constructed and sampled when interface type is AXI_ACE or AC_LITE and data_width is 64.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_ace_dweq_64bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_128bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_128bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 128. It is constructed and sampled when interface type is AXI3 and data_width is 128.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_128bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_32bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_32bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 32. It is constructed and sampled when interface type is AXI3 and data_width is 32.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_32bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_32bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_64bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_64bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 64. It is constructed and sampled when interface type is AXI3 and data_width is 64.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi3_dweq_64bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_128bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_128bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 128. It is constructed and sampled when interface type is AXI4 and data_width is 128.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_128bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_32bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_32bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 32. It is constructed and sampled when interface type is AXI4 and data_width is 32.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_32bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_64bit

Covergroup: trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_64bit

This cover group crosses bit AWCACHE[1] with unaligned write transfers for data_width 64. It is constructed and sampled when interface type is AXI4 and data_width is 64.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size
cache_type_modifiable_bit: Captures AWCACHE[1]

Cross coverpoints:

axi_awcache_modifiable_bit_write_unaligned_transfer_dweq_64bit: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A:4:4:2

covergroup trans_cross_axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type_modifiable_bit : coverpoint cov_item.cache_type[1] iff(cov_cache_type_flag){
    bins svt_axi_cache_modifiable_only = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awcache_modifiable_bit_write_unaligned_transfer_axi4_dweq_64bit : cross write_xact_type, burst_type, addr_offset, transfer_size, cache_type_modifiable_bit {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
     option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_ooo_write_response_depth

Covergroup: trans_cross_axi_ooo_write_response_depth

Coverpoints:

ooo_write_response : Captures out-of-order write response
ooo_write_response_depth : Captures out-of-order write response depth
- out-of-order response depth is determined by the position of the transaction in outstanding queue for which response is being returned. Ex: if outstanding queue has 5 entries and response is received for 4th transaction (i.e. entry[3]) then depth will be determined as "3" because, response for the first or head-of-ooo-queue transaction is not considered as out-of-order.
- User has option to modify each coverpoints through following defines.
  - VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
    
    _CG_ provides covergroup name and _CP_ provides coverpoint name. By default these are defined empty. User can just define above macros to ignore certain bin values or ignore all bins and define entirely customized set of bins. NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction fo this.
  - user can override the covergroup by extending the callback class and re-defining this covergroup
  - user can disable this covergroup and define their own covergroup extending this coverage callback class

covergroup trans_cross_axi_ooo_write_response_depth @ ( cov_out_of_order_write_response_depth_event ) ;
     ooo_write_response: coverpoint out_of_order_write_response_depth iff(out_of_order_write_response_depth_flag){
      bins ooo_depth = {[0:((cfg_num_outstanding_xact == -1)?cfg_num_write_outstanding_xact-1:cfg_num_outstanding_xact-1)]};
              option.weight = 1;
    }
    ooo_write_response_depth : coverpoint out_of_order_write_response_depth iff(out_of_order_write_response_depth_flag){
      bins ooo_depth[] = {[0:((cfg_num_outstanding_xact == -1)?cfg_num_write_outstanding_xact-1:cfg_num_outstanding_xact-1)]};
              option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_outstanding_xact

This covergroup captures attributes for total outstanding xact , outstanding write xact and outstanding read xact. It is constructed when trans_cross_axi_outstanding_xact_enable is set to 1.

Covergroup: trans_cross_axi_outstanding_xact

Coverpoints:

total_outstanding_xact : Captures total number of outstanding(read/write) transactions
outstanding_write_xact : Captures number of outstanding write transactions
outstanding_read_xact : Captures number of outstanding read transactions

covergroup trans_cross_axi_outstanding_xact(int num_outstanding_xacts, int num_write_outstanding_xacts, int num_read_outstanding_xacts) @ ( cov_outstanding_event ) ;
      total_outstanding_xact : coverpoint num_outstanding_xact iff(total_outstanding_xact_flag){
    bins total_outstanding_xact[] = {[1:num_outstanding_xacts]};
    option.weight = 1;
    type_option.weight = 1;
  }
     outstanding_write_xact : coverpoint num_write_outstanding_xact iff(outstanding_write_xact_flag){
    bins write_outstanding_xact[] = {[1:num_write_outstanding_xacts]};
    option.weight = 1;
    type_option.weight = 1;
  }
     outstanding_read_xact : coverpoint num_read_outstanding_xact iff(outstanding_read_xact_flag){
    bins read_outstanding_xact[] = {[1:num_read_outstanding_xacts]};
    option.weight = 1;
    type_option.weight = 1;
  }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_atomictype_cache_type_axi3

Covergroup: trans_cross_axi_read_atomictype_cache_type_axi3

This covergroup is cross coverage for read transactions of lock signal with all legel cache type values. The legal ARCACHE values for exclusive access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI4 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

covergroup trans_cross_axi_read_atomictype_cache_type_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins non_cacheable_non_bufferable = {0};
    bins bufferable_or_modifiable_only = {1};
    bins cacheable_but_no_alloc = {2};
    bins cacheable_bufferable_but_no_alloc = {3};
    bins cacheable_write_through_allocate_on_read_only = {6};
    bins cacheable_write_back_allocate_on_read_only = {7};
    bins cacheable_write_through_allocate_on_write_only = {10};
    bins cacheable_write_back_allocate_on_write_only = {11};
    bins cacheable_write_through_allocate_on_both_read_write = {14};
    bins cacheable_write_back_allocate_on_both_read_write = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_arcache : cross read_xact_type, atomic_type,cache_type{
       ignore_bins Ignore_invalid_cache_for_excl = binsof(atomic_type.exclusive) && !binsof(cache_type) intersect { 0, 1, 2, 3};
       option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_atomictype_cache_type_axi4

Covergroup: trans_cross_axi_read_atomictype_cache_type_axi4

This covergroup is cross coverage for read transactions of lock signal with all legel cache type values. The legal ARCACHE values for exclusive read exclusive access are

Device Non-bufferable
Device bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of ARCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI3 or AXI4 and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
read_xact_type: Captures read transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_exclusive_arcache: Crosses cover points read_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section A7.2.4

covergroup trans_cross_axi_read_atomictype_cache_type_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {10};
    bins write_through_read_allocate = {14};
    bins write_through_write_allocate = {10};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {11};
    bins write_back_read_allocate = {15};
    bins write_back_write_allocate = {11};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_atomictype_exclusive_arcache : cross read_xact_type, atomic_type,cache_type{
       ignore_bins Ignore_invalid_cache_for_excl = binsof(atomic_type.exclusive) && !binsof(cache_type) intersect { 0, 1, 2, 3};
       ignore_bins Ignore_locked = binsof(atomic_type.locked);
    option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_burst_type_len_atomictype_axi3

Covergroup: trans_cross_axi_read_burst_type_len_atomictype_axi3

This covergroup captures attributes of burst_type,burst_length and atomic_type for read transaction. It is constructed and sampled when interface_type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_read_burst_type_len_atomictype_axi3;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
    // ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1,`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_burst_type_len_atomictype_axi4

Covergroup: trans_cross_axi_read_burst_type_len_atomictype_axi4

This covergroup captures attributes of burst_type,burst_length and atomic_type for read transactions . It is constructed and sampled when interface_type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_arburst_arlen_arlock: Crosses cover points read_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_read_burst_type_len_atomictype_axi4;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_arburst_arlen_arlock : cross read_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_locked = binsof(atomic_type.locked);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_interleaving_depth

Covergroup: trans_cross_axi_read_interleaving_depth

This covergroup describes about interleave depth size for read transfer. It is constructed when trans_cross_axi_read_interleaving_depth_enable is asserted. The number of bins get hit is equal to the number of active read transactions that were interleaved.

Coverpoints:

read_data_interleave : Captures read data interleave depth

covergroup trans_cross_axi_read_interleaving_depth @ ( cov_interleave_depth_event ) ;
      read_data_interleave : coverpoint read_data_interleaving_depth iff(read_data_interleave_flag){
    bins read_data_interleave_size[] = {[1:4]};
    option.weight = 1;
    type_option.weight = 1;
  }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_128bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_128bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 128 bit. It is constrcuted and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_ace_dweq_128bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_256bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_256bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 256 bit. It is constrcuted and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 1;
  }
    axi_read_narrow_transfer_arlen_araddr_ace_dweq_256bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_32bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_32bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 32 bit. It is constrcuted and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_ace_dweq_32bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_512bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_512bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 512 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    bins offset_20 = {32};
    bins offset_21 = {33};
    bins offset_22 = {34};
    bins offset_23 = {35};
    bins offset_24 = {36};
    bins offset_25 = {37};
    bins offset_26 = {38};
    bins offset_27 = {39};
    bins offset_28 = {40};
    bins offset_29 = {41};
    bins offset_2a = {42};
    bins offset_2b = {43};
    bins offset_2c = {44};
    bins offset_2d = {45};
    bins offset_2e = {46};
    bins offset_2f = {47};
    bins offset_30 = {48};
    bins offset_31 = {49};
    bins offset_32 = {50};
    bins offset_33 = {51};
    bins offset_34 = {52};
    bins offset_35 = {53};
    bins offset_36 = {54};
    bins offset_37 = {55};
    bins offset_38 = {56};
    bins offset_39 = {57};
    bins offset_3a = {58};
    bins offset_3b = {59};
    bins offset_3c = {60};
    bins offset_3d = {61};
    bins offset_3e = {62};
    bins offset_3f = {63};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins xfer_size_64byte = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_ace_dweq_512bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_64bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_64bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 64 bit. It is constrcuted and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_ace_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_ace_dweq_64bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_128bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_128bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 128 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi3_dweq_128bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_256bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_256bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 256 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_256bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 1;
  }
    axi_read_narrow_transfer_arlen_araddr_axi3_dweq_256bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_32bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr

This Covergroup captures transfer size and address offset for read narrow transfer. It is constrcuted and sampled when trans_cross_axi_read_narrow_transfer_arlen_araddr_enable is asserted.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi3_dweq_32bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_512bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_512bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 512 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_512bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    bins offset_20 = {32};
    bins offset_21 = {33};
    bins offset_22 = {34};
    bins offset_23 = {35};
    bins offset_24 = {36};
    bins offset_25 = {37};
    bins offset_26 = {38};
    bins offset_27 = {39};
    bins offset_28 = {40};
    bins offset_29 = {41};
    bins offset_2a = {42};
    bins offset_2b = {43};
    bins offset_2c = {44};
    bins offset_2d = {45};
    bins offset_2e = {46};
    bins offset_2f = {47};
    bins offset_30 = {48};
    bins offset_31 = {49};
    bins offset_32 = {50};
    bins offset_33 = {51};
    bins offset_34 = {52};
    bins offset_35 = {53};
    bins offset_36 = {54};
    bins offset_37 = {55};
    bins offset_38 = {56};
    bins offset_39 = {57};
    bins offset_3a = {58};
    bins offset_3b = {59};
    bins offset_3c = {60};
    bins offset_3d = {61};
    bins offset_3e = {62};
    bins offset_3f = {63};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins xfer_size_64byte = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi3_dweq_512bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_64bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_64bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 64 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi3_dweq_64bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_128bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_128bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 128 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi4_dweq_128bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_32bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_64bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 32 bit. It is constrcuted and sampled when interface type is AXI4.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi4_dweq_32bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_64bit

Covergroup: trans_cross_axi_read_narrow_transfer_arlen_araddr_axi3_dweq_64bit

This Covergroup captures transfer size and address offset for read narrow transfer for when data width is 64 bit. It is constrcuted and sampled when interface type is AXI3.

Coverpoints:

read_xact_type: Captures read transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_read_narrow_transfer_arlen_araddr: Crosses cover points read_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_read_narrow_transfer_arlen_araddr_axi4_dweq_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_read_narrow_transfer_arlen_araddr_axi4_dweq_64bit : cross read_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_ace_dwlt_128bit

Covergroup: trans_cross_axi_read_unaligned_transfer_ace_dwlt_128bit

This Covergroup captures burst_type,burst_length, transfer size and address offset for read unaligned transfer when data width is less than 128 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_ace_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_ace_dwlt_32bit

Covergroup: trans_cross_axi_read_unaligned_transfer_ace_dwlt_32bit

This Covergroup captures burst_type,burst_length, transfer size and address offset for read unaligned transfer when data width is less than 32 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_ace_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_ace_dwlt_64bit

Covergroup: trans_cross_axi_read_unaligned_transfer_ace_dwlt_64bit

This Covergroup captures burst_type,burst_length, transfer size and address offset for read unaligned transfer when data width is less than 64 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_ace_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
      }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi3_dwlt_128bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi3_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi3_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi3_dwlt_32bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi3_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi3_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi3_dwlt_64bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi3_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi3_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi4_dwlt_128bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi4_dwlt_128bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi4_dwlt_128bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi4_dwlt_32bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi4_dwlt_32bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi4_dwlt_32bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_read_unaligned_transfer_axi4_dwlt_64bit

Covergroup: trans_cross_axi_read_unaligned_transfer_axi4_dwlt_64bit

Coverpoints:

read_xact_type: Captures read transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_read_unaligned_transfer: Crosses cover points read_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_read_unaligned_transfer_axi4_dwlt_64bit;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_read_unaligned_transfer : cross read_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_atomictype_cache_type_axi3

Covergroup: trans_cross_axi_write_atomictype_cache_type_axi3

This covergroup is cross coverage for write transactions of lock signal with legal all cache type values . The legal AWCACHE values for exclusive locked write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI3 and trans_cross_axi_atomictype_exclusive_awcache_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

covergroup trans_cross_axi_write_atomictype_cache_type_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins non_cacheable_non_bufferable = {0};
    bins bufferable_or_modifiable_only = {1};
    bins cacheable_but_no_alloc = {2};
    bins cacheable_bufferable_but_no_alloc = {3};
    bins cacheable_write_through_allocate_on_read_only = {6};
    bins cacheable_write_back_allocate_on_read_only = {7};
    bins cacheable_write_through_allocate_on_write_only = {10};
    bins cacheable_write_back_allocate_on_write_only = {11};
    bins cacheable_write_through_allocate_on_both_read_write = {14};
    bins cacheable_write_back_allocate_on_both_read_write = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_awcache : cross write_xact_type, atomic_type,cache_type{
       ignore_bins Ignore_invalid_cache_for_excl = binsof(atomic_type.exclusive) && !binsof(cache_type) intersect { 0, 1, 2, 3};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_atomictype_cache_type_axi4

Covergroup: trans_cross_axi_write_atomictype_cache_type_axi4

This covergroup is cross coverage of WRITE Exclusive Access with all legel AWCache values for exclusive access. The legal AWCACHE values for exclusive write access are

Device bufferable
Device Non-bufferable
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
The protocol permits using the bufferable versions of AWCACHE during exclusive accesses, but the system designer must ensure buffered exclusive accesses are still monitored by the slave i.e a more sensible design would be one where the buffer looks at the value of AxLOCK, and after seeing that the access is exclusive, decides to not return an early response. It is constructed and sampled when interface type is AXI3, AXI4 OR AXI4_LITE and trans_cross_axi_atomictype_exclusive_arcache_enable is asserted.
Coverpoints:
write_xact_type: Captures write transaction
atomic_type: Captures transaction atomic type
cache_type: Captures transaction cache type

Cross coverpoints:

axi_atomictype_awcache: Crosses cover points write_xact_type, atomic_type,cache_type.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; A7.2.4

covergroup trans_cross_axi_write_atomictype_cache_type_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
     cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins device_non_bufferable = {0};
    bins device_bufferable = {1};
    bins normal_non_cacheable_non_bufferable = {2};
    bins normal_non_cacheable_bufferable = {3};
    bins write_through_no_allocate = {6};
    bins write_through_read_allocate = {6};
    bins write_through_write_allocate = {14};
    bins write_through_read_and_write_allocate = {14};
    bins write_back_no_allocate = {7};
    bins write_back_read_allocate = {7};
    bins write_back_write_allocate = {15};
    bins write_back_read_and_write_allocate = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_atomictype_awcache : cross write_xact_type, atomic_type,cache_type{
       ignore_bins Ignore_invalid_cache_for_excl = binsof(atomic_type.exclusive) && !binsof(cache_type) intersect { 0, 1, 2, 3};
       ignore_bins Ignore_locked = binsof(atomic_type.locked);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_interleaving_depth

This covergroup captures attributes for write data interleave depth. It is constructed when interface type is set to AXI3 .

Covergroup: trans_cross_axi_write_interleaving_depth

Coverpoints:

write_data_interleave : Captures write data interleave depth

covergroup trans_cross_axi_write_interleaving_depth @ ( cov_interleave_depth_event ) ;
      write_data_interleave : coverpoint write_data_interleaving_depth iff(write_data_interleave_flag){
    bins write_data_interleave_depth[] = {[1:1]};
    option.weight = 1;
    type_option.weight = 1;
  }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi4_stream_interleaving_depth

Covergroup: trans_cross_axi4_stream_interleaving_depth

This covergroup describes about interleave depth size for axi_stream tb. It is constructed when interface type is AXI_STREAM

Coverpoints:

axi4_stream_interleave : Captures axi4 stream data interleave depth

covergroup trans_cross_axi4_stream_interleaving_depth @ ( cov_stream_interleave_depth_event ) ;
      axi4_stream_data_interleave : coverpoint axi4_stream_data_interleaving_depth iff(stream_data_interleave_flag){
    bins axi4_stream_data_interleave_size[] = {[1:4]};
    option.weight = 1;
    type_option.weight = 1;
  }
     option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_ooo_read_response_depth

Covergroup: trans_cross_axi_ooo_read_response_depth

This covergroup describes It is constructed when trans_cross_axi_ooo_read_response_depth_enable is asserted. Coverpoints:

ooo_read_response: Captures out-of-order read response
ooo_read_response_depth: Captures out-of-order read response depth
- out-of-order response depth is determined by the position of the transaction in outstanding queue for which response is being returned. Ex: if outstanding queue has 5 entries and response is received for 4th transaction (i.e. entry[3]) then depth will be determined as "3" because, response for the first or head-of-ooo-queue transaction is not considered as out-of-order.
- User has option to modify each coverpoints through following defines.
  - VIP Built-in IGNORE_BIN define: VIP provides following "define" macro
    
    _CG_ provides covergroup name and _CP_ provides coverpoint name. By default these are defined empty. User can just define above macros to ignore certain bin values or ignore all bins and define entirely customized set of bins. NOTE: ignore bin name is completely user defined, VIP doesn't have any restriction fo this.
  - user can override the covergroup by extending the callback class and re-defining this covergroup
  - user can disable this covergroup and define their own covergroup extending this coverage callback class

covergroup trans_cross_axi_ooo_read_response_depth @ ( cov_out_of_order_read_response_depth_event ) ;
     ooo_read_response: coverpoint out_of_order_read_response_depth iff(out_of_order_read_response_depth_flag){
      bins ooo_depth = {[0:((cfg_num_outstanding_xact == -1)?cfg_num_read_outstanding_xact-1:cfg_num_outstanding_xact-1)]};
              option.weight = 1;
    }
    ooo_read_response_depth : coverpoint out_of_order_read_response_depth iff(out_of_order_read_response_depth_flag){
      bins ooo_depth[] = {[0:((cfg_num_outstanding_xact == -1)?cfg_num_read_outstanding_xact-1:cfg_num_outstanding_xact-1)]};
              option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_burst_type_len_atomictype_axi3

Covergroup: trans_cross_axi_write_burst_type_len_atomictype_axi3

This covergroup describes about burst_type,burst_length and lock signal for write transfer. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_write_burst_type_len_atomictype_axi3;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:16]};
      ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      //ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1,`SVT_AXI_WRAP_BURST_LENGTH_RANGE};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_burst_type_len_atomictype_axi4

Covergroup: trans_cross_axi_write_burst_type_len_atomictype_axi4

This covergroup describes about burst_type,burst_length and lock signal write transfer. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
burst_length: Captures transaction burst length
atomic_type: Captures transaction atomic type

Cross coverpoints:

axi_awburst_awlen_awlock: Crosses cover points write_xact_type, burst_type, burst_length, atomic_type

covergroup trans_cross_axi_write_burst_type_len_atomictype_axi4;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
        bins burst_length[4] = {[1:256]};
      ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
      option.weight = 0;
    type_option.weight = 0;
  }
     atomic_type : coverpoint cov_item.atomic_type iff(cov_atomic_type_flag){
    bins normal = {svt_axi_transaction::NORMAL};
    bins exclusive = {svt_axi_transaction::EXCLUSIVE};
    bins locked = {svt_axi_transaction::LOCKED};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_awburst_awlen_awlock : cross write_xact_type, burst_type, burst_length, atomic_type{
      ignore_bins Ignore_invalid_excl_burst = binsof(atomic_type.exclusive) && !binsof(burst_length) intersect {1, 2,4,8,16};
      ignore_bins Ignore_invalid_wrap = binsof(burst_type.wrap_burst) && !binsof(burst_length) intersect { 2,4,8,16};
      ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(burst_length) intersect {[ 17: ((1<<10))]};
      ignore_bins Ignore_locked = binsof(atomic_type.locked);
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_128bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_128bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 128 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_ace_dweq_128bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_256bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_256bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 256 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 1;
  }
    axi_write_narrow_transfer_awlen_awaddr_ace_dweq_256bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_32bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_32bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 32 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_ace_dweq_32bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_512bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_512bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 512 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    bins offset_20 = {32};
    bins offset_21 = {33};
    bins offset_22 = {34};
    bins offset_23 = {35};
    bins offset_24 = {36};
    bins offset_25 = {37};
    bins offset_26 = {38};
    bins offset_27 = {39};
    bins offset_28 = {40};
    bins offset_29 = {41};
    bins offset_2a = {42};
    bins offset_2b = {43};
    bins offset_2c = {44};
    bins offset_2d = {45};
    bins offset_2e = {46};
    bins offset_2f = {47};
    bins offset_30 = {48};
    bins offset_31 = {49};
    bins offset_32 = {50};
    bins offset_33 = {51};
    bins offset_34 = {52};
    bins offset_35 = {53};
    bins offset_36 = {54};
    bins offset_37 = {55};
    bins offset_38 = {56};
    bins offset_39 = {57};
    bins offset_3a = {58};
    bins offset_3b = {59};
    bins offset_3c = {60};
    bins offset_3d = {61};
    bins offset_3e = {62};
    bins offset_3f = {63};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins xfer_size_64byte = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_ace_dweq_512bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_64bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_64bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 64 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_ace_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_ace_dweq_64bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_128bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_128bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 128 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_128bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_256bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_256bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 256 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_256bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    option.weight = 1;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_256bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_32bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaadr_axi3_dweq_32bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 32 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_32bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_512bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_512bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 512 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_512bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    bins offset_10 = {16};
    bins offset_11 = {17};
    bins offset_12 = {18};
    bins offset_13 = {19};
    bins offset_14 = {20};
    bins offset_15 = {21};
    bins offset_16 = {22};
    bins offset_17 = {23};
    bins offset_18 = {24};
    bins offset_19 = {25};
    bins offset_1a = {26};
    bins offset_1b = {27};
    bins offset_1c = {28};
    bins offset_1d = {29};
    bins offset_1e = {30};
    bins offset_1f = {31};
    bins offset_20 = {32};
    bins offset_21 = {33};
    bins offset_22 = {34};
    bins offset_23 = {35};
    bins offset_24 = {36};
    bins offset_25 = {37};
    bins offset_26 = {38};
    bins offset_27 = {39};
    bins offset_28 = {40};
    bins offset_29 = {41};
    bins offset_2a = {42};
    bins offset_2b = {43};
    bins offset_2c = {44};
    bins offset_2d = {45};
    bins offset_2e = {46};
    bins offset_2f = {47};
    bins offset_30 = {48};
    bins offset_31 = {49};
    bins offset_32 = {50};
    bins offset_33 = {51};
    bins offset_34 = {52};
    bins offset_35 = {53};
    bins offset_36 = {54};
    bins offset_37 = {55};
    bins offset_38 = {56};
    bins offset_39 = {57};
    bins offset_3a = {58};
    bins offset_3b = {59};
    bins offset_3c = {60};
    bins offset_3d = {61};
    bins offset_3e = {62};
    bins offset_3f = {63};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins xfer_size_32byte = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins xfer_size_64byte = {svt_axi_transaction::BURST_SIZE_512BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_512bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_64bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_64bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is less 64 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_64bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_128bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_128bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 128 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_128bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_32bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_32bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 32 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_32bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_64bit

Covergroup: trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi3_dweq_64bit

This Covergroup captures write_xact_type ,transfer size and address offset for narrow transfer and data width is 64 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
transfer_size: Captures transaction burst size
addr_offset: Captures transaction address offset information

Cross coverpoints:

axi_write_narrow_transfer_awlen_awaddr: Crosses cover points write_xact_type,transfer_size,addr_offset

covergroup trans_cross_axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
    axi_write_narrow_transfer_awlen_awaddr_axi4_dweq_64bit : cross write_xact_type,transfer_size,addr_offset {
      option.weight = 1;
    }
    option.per_instance = 1;
  endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_ace_dwlt_128bit

Covergroup: trans_cross_axi_write_unaligned_transfer_ace_dwlt_128bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 128 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

ace_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_ace_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_ace_dwlt_32bit

Covergroup: trans_cross_axi_write_unaligned_transfer_ace_dwlt_32bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 32 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

ace_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_ace_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     ace_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_ace_dwlt_64bit

Covergroup: trans_cross_axi_write_unaligned_transfer_ace_dwlt_64bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 64 bit. It is constructed and sampled when interface type is AXI_ACE or ACE_LITE.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

ace_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_ace_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     ace_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi3_dwlt_128bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi3_dwlt_128bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 128 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi3_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi3_dwlt_32bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi3_dwlt_32bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 32 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi3_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi3_dwlt_64bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi3_dwlt_64bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 64 bit. It is constructed and sampled when interface type is AXI3.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi3_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi4_dwlt_128bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi4_dwlt_128bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 128 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi4_dwlt_128bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    bins offset_8 = {8};
    bins offset_9 = {9};
    bins offset_a = {10};
    bins offset_b = {11};
    bins offset_c = {12};
    bins offset_d = {13};
    bins offset_e = {14};
    bins offset_f = {15};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins xfer_size_16byte = {svt_axi_transaction::BURST_SIZE_128BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_16_Bxfer_128dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_16byte));
  ignore_bins Ig_algn_8_Bxfer_128dw = ((binsof(addr_offset)intersect {0,['h8:'hf]}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[4:'hf]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_128dw = ((binsof(addr_offset)intersect {0,[2:'hf]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi4_dwlt_32bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi4_dwlt_32bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 32 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi4_dwlt_32bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_4_Bxfer32dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_32dw = ((binsof(addr_offset)intersect {0,[2:3]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_axi_write_unaligned_transfer_axi4_dwlt_64bit

Covergroup: trans_cross_axi_write_unaligned_transfer_axi4_dwlt_64bit

This Covergrpoup captures following signals for unaligned write transfer when data width is less than 64 bit. It is constructed and sampled when interface type is AXI4.

Coverpoints:

write_xact_type: Captures write transaction
burst_type: Captures transaction burst type
addr_offset: Captures transaction address offset information
transfer_size: Captures transaction burst size

Cross coverpoints:

axi_write_unaligned_transfer: Crosses cover points write_xact_type, burst_type, addr_offset, transfer_size

covergroup trans_cross_axi_write_unaligned_transfer_axi4_dwlt_64bit;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0 ;
    type_option.weight = 0;
  }
     burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
     addr_offset : coverpoint addr_offset_coverpoint iff(cov_addr_flag == 1'b1) {
    bins offset_0 = {0};
    bins offset_1 = {1};
    bins offset_2 = {2};
    bins offset_3 = {3};
    bins offset_4 = {4};
    bins offset_5 = {5};
    bins offset_6 = {6};
    bins offset_7 = {7};
    option.weight = 0;
    type_option.weight = 0;
  }
     transfer_size : coverpoint cov_item.burst_size iff(cov_burst_size_flag){
    bins xfer_size_1byte = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins xfer_size_2byte = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins xfer_size_4byte = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins xfer_size_8byte = {svt_axi_transaction::BURST_SIZE_64BIT};
    option.weight = 0;
    type_option.weight = 0;
  }
     axi_write_unaligned_transfer : cross write_xact_type, burst_type, addr_offset, transfer_size {
       ignore_bins ignore_unsupported_burst_type = binsof(burst_type) intersect {svt_axi_transaction::WRAP};
  ignore_bins ignore_aligned_addr_offset_0 = binsof(addr_offset) intersect {0};
  ignore_bins ignore_aligned_transfer_size = binsof(transfer_size) intersect {svt_axi_transaction::BURST_SIZE_8BIT};
  ignore_bins Ig_algn_8_Bxfer_64dw = ((binsof(addr_offset)intersect {0}) && binsof(transfer_size.xfer_size_8byte));
  ignore_bins Ig_algn_4_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[4:7]}) && binsof(transfer_size.xfer_size_4byte));
  ignore_bins Ig_algn_2_Bxfer_64dw = ((binsof(addr_offset)intersect {0,[2:7]}) && binsof(transfer_size.xfer_size_2byte));
       ignore_bins ignore_4k_boundary_cross = (binsof(addr_offset) && binsof(transfer_size) && binsof(burst_type)) iff(is_addr_4kb_boundary_cross_flag == 1 || 12 > 12);
        option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

arvalid : Captures ARVALID == 1
arready_0 : Captures ARREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop : Crosses coverpoints arvaild and arready_0 and acvalid and acready and acsnoop

covergroup trans_cross_dvm_overlap_arvalid_arready_cover_acvalid_acready_acsnoop @ ( dvm_overlap_scenarios_snoop_addr_event ) ;
       arvalid : coverpoint axi_monitor_mp.axi_monitor_cb.arvalid {
   bins arvalid_val = {1};
   option.weight = 0;
   }
     arready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.arready {
   bins arready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acvalid : coverpoint axi_monitor_mp.axi_monitor_cb.acvalid {
   bins acvalid_val_1 = {1};
   bins acvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acready : coverpoint axi_monitor_mp.axi_monitor_cb.acready {
   bins acready_val_1 = {1};
   bins acready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acsnoop : coverpoint axi_monitor_mp.axi_monitor_cb.acsnoop {
   bins acsnoop_val = {4'b1110 ,4'b1111};
   option.weight = 0;
   type_option.weight = 0;
   }
     overlap_case_dvm_arvalid_arready_acvalid_acready_acsnoop : cross arvalid, arready_0, acvalid, acready, acsnoop {
      ignore_bins Ignore_acvalid_val = binsof(acvalid) intersect {0};
      ignore_bins Ignore_acready_val = binsof(acready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready

Covergroup: trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when ARVALID == 1 and ARREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

arvalid : Captures ARVALID == 1
arready_0 : Captures ARREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_arvalid_high_arready_low_crvalid_crready : Crosses coverpoints arvalid and arready_0 and crvalid and crready

covergroup trans_cross_dvm_overlap_arvalid_arready_cover_crvalid_crready @ ( dvm_overlap_scenarios_snoop_resp_event ) ;
       arvalid : coverpoint axi_monitor_mp.axi_monitor_cb.arvalid {
   bins arvalid_val = {1};
   option.weight = 0;
   }
     arready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.arready {
   bins arready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crvalid : coverpoint axi_monitor_mp.axi_monitor_cb.crvalid {
   bins crvalid_val_1 = {1};
   bins crvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crready : coverpoint axi_monitor_mp.axi_monitor_cb.crready {
   bins crready_val_1 = {1};
   bins crready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
        overlap_case_dvm_arvalid_high_arready_low_crvalid_crready : cross arvalid, arready_0, crvalid, crready {
      ignore_bins Ignore_crvalid_val = binsof(crvalid) intersect {0};
      ignore_bins Ignore_crready_val = binsof(crready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

awvalid : Captures AWVALID == 1
awready_0 : Captures AWREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop : Crosse coverpoints awvalid and awready_0 and acvalid and acready and acsnoop

covergroup trans_cross_dvm_overlap_awvalid_awready_cover_acvalid_acready_acsnoop @ ( dvm_overlap_scenarios_snoop_addr_event ) ;
       awvalid : coverpoint axi_monitor_mp.axi_monitor_cb.awvalid {
   bins awvalid_val = {1};
   option.weight = 1 ;
   }
     awready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.awready {
   bins awready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acvalid : coverpoint axi_monitor_mp.axi_monitor_cb.acvalid {
   bins acvalid_val_1 = {1};
   bins acvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acready : coverpoint axi_monitor_mp.axi_monitor_cb.acready {
   bins acready_val_1 = {1};
   bins acready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acsnoop : coverpoint axi_monitor_mp.axi_monitor_cb.acsnoop {
   bins acsnoop_val = {4'b1110 ,4'b1111};
   option.weight = 0;
   type_option.weight = 0;
   }
     overlap_case_dvm_awvalid_high_awready_low_acvalid_acready_acsnoop : cross awvalid, awready_0 ,acvalid, acready, acsnoop {
      ignore_bins Ignore_acvalid_val = binsof(acvalid) intersect {0};
      ignore_bins Ignore_acready_val = binsof(acready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready

Covergroup: trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when AWVALID == 1 & AWREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

awvalid : Captures AWVALID == 1
awready_0 : Captures AWREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_awvalid_high_awready_low_crvalid_crready : Crosses coverpoints awvalid and awready_0 and crvalid and crready

covergroup trans_cross_dvm_overlap_awvalid_awready_cover_crvalid_crready @ ( dvm_overlap_scenarios_snoop_resp_event ) ;
       awvalid : coverpoint axi_monitor_mp.axi_monitor_cb.awvalid {
   bins awvalid_val = {1};
   option.weight = 1 ;
   }
     awready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.awready {
   bins awready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crvalid : coverpoint axi_monitor_mp.axi_monitor_cb.crvalid {
   bins crvalid_val_1 = {1};
   bins crvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crready : coverpoint axi_monitor_mp.axi_monitor_cb.crready {
   bins crready_val_1 = {1};
   bins crready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     overlap_case_dvm_awvalid_high_awready_low_crvalid_crready : cross awvalid, awready_0, crvalid, crready {
      ignore_bins Ignore_crvalid_val = binsof(crvalid) intersect {0};
      ignore_bins Ignore_crready_val = binsof(crready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

bvalid_1 : Captures BVALID == 1
bready_0 : Captures BREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop : Crosses coverpoints bvalid_1 and bready_0 and acvalid and acready and acsnoop

covergroup trans_cross_dvm_overlap_bvalid_bready_cover_acvalid_acready_acsnoop @ ( dvm_overlap_scenarios_snoop_addr_event ) ;
      bvalid_1 : coverpoint axi_monitor_mp.axi_monitor_cb.bvalid {
   bins bvalid_val_1 = {1};
   option.weight = 0;
   type_option.weight = 0;
   }
     bready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.bready {
   bins bready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acvalid : coverpoint axi_monitor_mp.axi_monitor_cb.acvalid {
   bins acvalid_val_1 = {1};
   bins acvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acready : coverpoint axi_monitor_mp.axi_monitor_cb.acready {
   bins acready_val_1 = {1};
   bins acready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acsnoop : coverpoint axi_monitor_mp.axi_monitor_cb.acsnoop {
   bins acsnoop_val = {4'b1110 ,4'b1111};
   option.weight = 0;
   type_option.weight = 0;
   }
      overlap_case_dvm_bvalid_high_bready_low_acvalid_acready_acsnoop : cross bvalid_1, bready_0, acvalid, acready, acsnoop {
      ignore_bins Ignore_acvalid_val = binsof(acvalid) intersect {0};
      ignore_bins Ignore_acready_val = binsof(acready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready

Covergroup: trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when BVALID == 1 & BREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

bvalid_1 : Captures BVALID == 1
bready_0 : Captures BREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_bvalid_high_bready_low_crvalid_crready : Crosses coverpoints bvalid_1 and bready_0 and crvalid and crready

covergroup trans_cross_dvm_overlap_bvalid_bready_cover_crvalid_crready @ ( dvm_overlap_scenarios_snoop_resp_event ) ;
      bvalid_1 : coverpoint axi_monitor_mp.axi_monitor_cb.bvalid {
   bins bvalid_val_1 = {1};
   option.weight = 0;
   type_option.weight = 0;
   }
     bready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.bready {
   bins bready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crvalid : coverpoint axi_monitor_mp.axi_monitor_cb.crvalid {
   bins crvalid_val_1 = {1};
   bins crvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crready : coverpoint axi_monitor_mp.axi_monitor_cb.crready {
   bins crready_val_1 = {1};
   bins crready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
          overlap_case_dvm_bvalid_high_bready_low_crvalid_crready : cross bvalid_1, bready_0, crvalid, crready {
      ignore_bins Ignore_crvalid_val = binsof(crvalid) intersect {0};
      ignore_bins Ignore_crready_val = binsof(crready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop

Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop

This covergroup captures coverage related to DVM overlap case to cover acvalid=1 & acready=1 & acsnoop=dvm when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

rvalid_1 : Captures RVALID == 1
rready_0 : Captures RREADY == 0
acvalid : Captures ACVALID == 1
acready : Captures ACREADY == 1
acsnnop : Captures ACSNOOP == DVM

Cross coverpoints:

overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop : Crosses coverpoints rvalid_1 and rready_0 and acvalid and cready and acsnoop

covergroup trans_cross_dvm_overlap_rvalid_rready_cover_acvalid_acready_acsnoop @ ( dvm_overlap_scenarios_snoop_addr_event ) ;
      rvalid_1 : coverpoint axi_monitor_mp.axi_monitor_cb.rvalid {
   bins rvalid_val_1 = {1};
   option.weight = 0;
   type_option.weight = 0;
   }
     rready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.rready {
   bins rready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acvalid : coverpoint axi_monitor_mp.axi_monitor_cb.acvalid {
   bins acvalid_val_1 = {1};
   bins acvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acready : coverpoint axi_monitor_mp.axi_monitor_cb.acready {
   bins acready_val_1 = {1};
   bins acready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     acsnoop : coverpoint axi_monitor_mp.axi_monitor_cb.acsnoop {
   bins acsnoop_val = {4'b1110 ,4'b1111};
   option.weight = 0;
   type_option.weight = 0;
   }
     overlap_case_dvm_rvalid_high_rready_low_acvalid_acready_acsnoop : cross rvalid_1, rready_0, acvalid, acready, acsnoop {
      ignore_bins Ignore_acvalid_val = binsof(acvalid) intersect {0};
      ignore_bins Ignore_acready_val = binsof(acready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready

Covergroup: trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready

This covergroup captures coverage related to DVM overlap case to cover crvalid=1 & crready=1 when RVALID == 1 & RREADY == 0. It is constructed when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: dvm_enable = 1.

Coverpoints:

rvalid_1 : Captures RVALID == 1
rready_0 : Captures RREADY == 0
crvalid : Captures CRVALID == 1
crready : Captures CRREADY == 1

Cross coverpoints:

overlap_case_dvm_rvalid_high_rready_low_crvalid_crready : Crosses coverpoints rvalid_1 and rready_0 and crvalid and crready

covergroup trans_cross_dvm_overlap_rvalid_rready_cover_crvalid_crready @ ( dvm_overlap_scenarios_snoop_resp_event ) ;
      rvalid_1 : coverpoint axi_monitor_mp.axi_monitor_cb.rvalid {
   bins rvalid_val_1 = {1};
   option.weight = 0;
   type_option.weight = 0;
   }
     rready_0 : coverpoint axi_monitor_mp.axi_monitor_cb.rready {
   bins rready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crvalid : coverpoint axi_monitor_mp.axi_monitor_cb.crvalid {
   bins crvalid_val_1 = {1};
   bins crvalid_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
     crready : coverpoint axi_monitor_mp.axi_monitor_cb.crready {
   bins crready_val_1 = {1};
   bins crready_val_0 = {0};
   option.weight = 0;
   type_option.weight = 0;
   }
       overlap_case_dvm_rvalid_high_rready_low_crvalid_crready : cross rvalid_1, rready_0, crvalid, crready {
      ignore_bins Ignore_crvalid_val = binsof(crvalid) intersect {0};
      ignore_bins Ignore_crready_val = binsof(crready) intersect {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_exclusive_writenosnoop_domain_type

Covergroup : trans_cross_exclusive_writenosnoop_domain_type

This Covergroup captures coherant writenosnoop_xact_type,write_resp and domain_type for write transaction. It is constructed and sampled when trans_cross_exclusive_writenosnoop_domain_type_enable and exclusive_access_enable is set to 1.

Coverpoints:

coherent_write_xact_type: Captures coherent writenosnoop transaction
bresp : Captures exokay write response
domain_type : Captures NONSHAREABLE & SYSTEMSHAREABLE domain types

Cross coverpoints:

awsnoop_awdomain_bresp : Crosses cover points coherent_write_xact_type, domain_type and bresp

The EXOKAY response is permitted for WriteNoSnoop with domain innershareable & outershareable. Rest all other bins are ignored.

covergroup trans_cross_exclusive_writenosnoop_domain_type;
     // Only WRITENOSNOOP is covered by this group. So cover only that
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_COHERENT_WRITE_XACT_TYPE
    coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
      bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
      option.weight = 0;
    }
    // Only EXOKAY response is being covered by this; so create covergroup only for that
    //`SVT_AXI_PORT_MONITOR_DEF_COV_UTIL_BRESP(`SVT_AXI_COV_WEIGHT_VAL_0)
    bresp : coverpoint cov_item.bresp iff(cov_bresp_flag){
      bins exokay_resp = {svt_axi_transaction::EXOKAY};
      option.weight = 0;
    }
    domain_type : coverpoint cov_item.domain_type iff(cov_domain_type_flag){
      bins domain_non_shareable = {svt_axi_transaction::NONSHAREABLE};
      bins domain_system_shareable = {svt_axi_transaction::SYSTEMSHAREABLE};
      option.weight = 0;
    }
     awsnoop_awdomain_bresp : cross coherent_write_xact_type, bresp, domain_type {
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_master_to_slave_path_access_ace

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI_ACE or ACE_LITE and trans_cross_master_to_slave_path_access_ace_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_ace

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_master_to_slave_path_access_ace @ ( cov_master_to_slave_access_event ) ;
      coherent_read_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_readnosnoop_xact = {svt_axi_transaction::READNOSNOOP};
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins coherent_dvmcomplete_xact = {svt_axi_transaction::DVMCOMPLETE};
    bins coherent_dvmmessage_xact = {svt_axi_transaction::DVMMESSAGE};
    bins coherent_readbarrier_xact = {svt_axi_transaction::READBARRIER};
    ignore_bins ignore_coh_read_xact_ace_lite = {svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY,
                                                 svt_axi_transaction::READUNIQUE,svt_axi_transaction::CLEANUNIQUE,
                                                 svt_axi_transaction::MAKEUNIQUE,svt_axi_transaction::READSHARED,
                                                 svt_axi_transaction::DVMCOMPLETE,svt_axi_transaction::DVMMESSAGE}
                                                   iff(cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE);
    ignore_bins ignore_barrier = {svt_axi_transaction::READBARRIER} iff(cfg.barrier_enable == 1'b0);
    ignore_bins ignore_dvm = {svt_axi_transaction::DVMMESSAGE,svt_axi_transaction::DVMCOMPLETE} iff(cfg.dvm_enable == 1'b0);
    option.weight = 1;
    type_option.weight = 1;
  }
     coherent_write_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_xact_type_flag){
    bins coherent_writenosnoop_xact = {svt_axi_transaction::WRITENOSNOOP};
    bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
    bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
    bins coherent_writeclean_xact = {svt_axi_transaction::WRITECLEAN};
    bins coherent_writeback_xact = {svt_axi_transaction::WRITEBACK};
    bins coherent_evict_xact = {svt_axi_transaction::EVICT};
    bins coherent_writebarrier_xact = {svt_axi_transaction::WRITEBARRIER};
    bins coherent_writeevict_xact = {svt_axi_transaction::WRITEEVICT};
    ignore_bins ignore_coh_write_xact_ace_lite = {svt_axi_transaction::WRITECLEAN,svt_axi_transaction::WRITEBACK,
                                                  svt_axi_transaction::EVICT}
                                                   iff(cfg.axi_interface_type == svt_axi_port_configuration::ACE_LITE);
    ignore_bins ignore_barrier = {svt_axi_transaction::WRITEBARRIER} iff(cfg.barrier_enable == 1'b0);
    ignore_bins ignore_writeevict = {svt_axi_transaction::WRITEEVICT} iff(cfg.writeevict_enable == 1'b0);
    option.weight = 1;
    type_option.weight = 1;
  }
     all_slaves : coverpoint path_cov_dest_names {
     bins slvs_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins[] = ignore_slaves_list;
      option.weight = 0;
    }
     slaves_excluding_register_space : coverpoint path_cov_dest_names {
     bins slvs_no_cfg_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins_no_cfg [] = ignore_cfg_slaves_list;
      option.weight = 0;
    }
     cross_read_xact_type_with_slave : cross all_slaves, coherent_read_xact_type ;
    cross_write_xact_type_with_slave : cross all_slaves, coherent_write_xact_type ;
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_master_to_slave_path_access_axi3

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI3 and trans_cross_master_to_slave_path_access_axi3_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_axi3

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_master_to_slave_path_access_axi3 @ ( cov_master_to_slave_access_event ) ;
      all_slaves : coverpoint path_cov_dest_names {
     bins slvs_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins[] = ignore_slaves_list;
      option.weight = 1;
    }
     slaves_excluding_register_space : coverpoint path_cov_dest_names {
     bins slvs_no_cfg_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins_no_cfg [] = ignore_cfg_slaves_list;
      option.weight = 1;
    }
           write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 1;
    type_option.weight = 1;
  }
           read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 1;
    type_option.weight = 1;
  }
      axi_ex_xact_type : coverpoint cov_item.atomic_type iff (cfg.exclusive_access_enable == 1){
    bins exclusive_type = {svt_axi_transaction::EXCLUSIVE} ;
    option.weight = 1;
    type_option.weight = 1;
  }
          atomic_type : coverpoint cov_item.atomic_type {
    bins normal = {svt_axi_transaction::NORMAL};
    bins locked = {svt_axi_transaction::LOCKED};
    ignore_bins atomic_type_axi4 = {svt_axi_transaction::LOCKED}iff((cfg.axi_interface_type == svt_axi_port_configuration::AXI4)||(cfg.locked_access_enable == 0));
    option.weight = 1;
    type_option.weight = 1;
  }
           burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 1;
    type_option.weight = 1;
  }
      axi_burst_size : coverpoint cov_item.burst_size {
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    bins burst_size_2048bit = {svt_axi_transaction::BURST_SIZE_2048BIT};
    bins burst_size_4096bit = {svt_axi_transaction::BURST_SIZE_4096BIT};
           option.weight = 1;
    type_option.weight = 1;
  }
       cache_type : coverpoint cov_item.cache_type iff(cov_cache_type_flag){
    bins non_cacheable_non_bufferable = {0};
    bins bufferable_or_modifiable_only = {1};
    bins cacheable_but_no_alloc = {2};
    bins cacheable_bufferable_but_no_alloc = {3};
    bins cacheable_write_through_allocate_on_read_only = {6};
    bins cacheable_write_back_allocate_on_read_only = {7};
    bins cacheable_write_through_allocate_on_write_only = {10};
    bins cacheable_write_back_allocate_on_write_only = {11};
    bins cacheable_write_through_allocate_on_both_read_write = {14};
    bins cacheable_write_back_allocate_on_both_read_write = {15};
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
    option.weight = 1;
    type_option.weight = 1;
  }
          axi_burst_len : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi3 = {[16+1:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
           axi_response_type : coverpoint m_response_type {
    bins axi_okay_response = {'b00};
    bins axi_exokay_response = {'b01};
    bins axi_slverr_response = {'b10};
    bins axi_decerr_response = {'b11};
    bins axi_exokay_fail_response = {'b00} iff(cfg.exclusive_access_enable == 1);
    option.weight = 1;
    type_option.weight = 1;
  }
          axi_address_aligned : coverpoint m_address_aligned {
    wildcard bins axi_8bit_aligned_address ={6'b?????1};
    wildcard bins axi_16bit_aligned_address ={6'b????1?};
    wildcard bins axi_32bit_aligned_address ={6'b???1??};
    wildcard bins axi_64bit_aligned_address ={6'b??1???};
    wildcard bins axi_128bit_aligned_address ={6'b?1????};
    wildcard bins axi_256bit_aligned_address ={6'b1?????};
    option.weight = 1;
    type_option.weight = 1;
  }
            axi_wstrb_beat_0 : coverpoint cov_item.wstrb[0] iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
                  option.weight = 0;
    }
       axi_wstrb_beat_1: coverpoint cov_item.wstrb[1] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h1) {
               option.weight = 0;
    }
     axi_wstrb_beat_2: coverpoint cov_item.wstrb[2] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h2) {
               option.weight = 0;
    }
     axi_wstrb_beat_3: coverpoint cov_item.wstrb[3] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h3) {
               option.weight = 0;
    }
     axi_wstrb_beat_15: coverpoint cov_item.wstrb[15] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length == 4'hf) {
               option.weight = 0;
    }
     //crosses the above coverpoints with all_slaves and slaves_excluding
    //register_space
     cache_len_1_all_okay : cross all_slaves, write_xact_type,read_xact_type,cache_type,axi_burst_len,axi_burst_size,axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_len_reduced_all_okay: cross slaves_excluding_register_space,cache_type,write_xact_type,read_xact_type,burst_type,axi_burst_len,axi_response_type {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]};
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_len_reduced_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, burst_type {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h2,[4'h4:4'h6],[4'h8:4'he]};
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h10)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_all_okay_fixed:cross slaves_excluding_register_space,cache_type,axi_burst_size,burst_type,axi_burst_len,axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
          cache_all_slverr_fixed:cross slaves_excluding_register_space, cache_type, axi_burst_size, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_ignore_resp_fixed:cross all_slaves, cache_type, axi_burst_len, axi_burst_size, burst_type {
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_all_okay_fixed_unaligned:cross slaves_excluding_register_space, cache_type, axi_address_aligned, axi_burst_size, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_ignore_resp_fixed_unaligned:cross all_slaves, cache_type, axi_address_aligned, axi_burst_size, axi_burst_len, burst_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
       master_to_slave_all_okay: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_burst_size, axi_response_type,burst_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, axi_burst_size, burst_type {
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_decerr_len_1: cross slaves_excluding_register_space, write_xact_type,read_xact_type, cache_type, axi_burst_len, axi_burst_size, axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_once_decerr = ! binsof (axi_response_type.axi_decerr_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_slverr_len_1: cross slaves_excluding_register_space, cache_type, axi_burst_len, axi_burst_size, axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_once_slverr = ! binsof (axi_response_type.axi_slverr_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_decerr: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type {
    ignore_bins axi_ignore_resp_except_once_decerr = ! binsof (axi_response_type.axi_decerr_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_slverr: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type {
    ignore_bins axi_ignore_resp_except_once_slverr = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
   }
              master_to_all_slave_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, burst_type {
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cross_xact_type_len_1_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_2_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_1 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_for_beat2 = binsof (axi_burst_len) intersect {4'h1};
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_3_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_2 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_len2_for_beat3 = binsof (axi_burst_len) intersect {4'h1,4'h2};
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_4_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_3 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_len2_len3_for_beat4 = binsof (axi_burst_len) intersect {4'h1,4'h2,4'h3};
    option.weight = 1;
    type_option.weight = 1;
  }
            cross_xact_type_len_16_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_15 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_all_len_except_len16_for_beat16 = binsof (axi_burst_len) intersect {[4'h1:4'hf]};
    option.weight = 1;
    type_option.weight = 1;
  }
            cross_aligned_unaligned_addr_asize: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_size, axi_address_aligned, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]};
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
            cross_aligned_unaligned_addr_asize_ignore_resp: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_size, axi_address_aligned, burst_type, axi_burst_len {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h2,[4'h4:4'h6],[4'h8:4'he]};
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
           master_to_slave_x_wr_okay_addr_align: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay = ! binsof (axi_response_type.axi_exokay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_x_wr_fail_addr_align: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay_fail = ! binsof (axi_response_type.axi_exokay_fail_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
         master_to_slave_x_wr_decerr: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_decerr = ! binsof (axi_response_type.axi_decerr_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_x_wr_slverr: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_slverr = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
          master_to_slave_x_wr_okay_wstrb: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_response_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay = ! binsof (axi_response_type.axi_exokay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_read_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
             master_to_slave_x_wr_fail_wstrb: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_response_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay_fail = ! binsof (axi_response_type.axi_exokay_fail_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_read_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
         option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_master_to_slave_path_access_axi4

This Covergroup captures attributes for coherant read and write type, for all slaves It is constructed when interface type is AXI4 and trans_cross_master_to_slave_path_access_axi4_enable is set to 1. Covergroup: trans_cross_master_to_slave_path_access_axi4

Coverpoints:

all_slaves : Captures all participating path cov slaves
slaves_excluding_register_space : Captures all non axi/ace register address space slaves
coherent_read_xact_type: Captures readonce coherent read transaction
coherent_write_xact_type: Captures coherent write transaction

Cross coverpoints:

cross_read_xact_type_with_slave : Crosses cover points all_slaves and coherent_read_xact_type
cross_write_xact_type_with_slave : Crosses cover points all_slaves and coherent_write_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.6

covergroup trans_cross_master_to_slave_path_access_axi4 @ ( cov_master_to_slave_access_event ) ;
      all_slaves : coverpoint path_cov_dest_names {
     bins slvs_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins[] = ignore_slaves_list;
      option.weight = 1;
    }
     slaves_excluding_register_space : coverpoint path_cov_dest_names {
     bins slvs_no_cfg_b[] = { [path_cov_dest_names_first:path_cov_dest_names_last] };
    ignore_bins ig_bins_no_cfg [] = ignore_cfg_slaves_list;
      option.weight = 1;
    }
          write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 1;
    type_option.weight = 1;
  }
          read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 1;
    type_option.weight = 1;
  }
      axi_ex_xact_type : coverpoint cov_item.atomic_type iff (cfg.exclusive_access_enable == 1){
    bins exclusive_type = {svt_axi_transaction::EXCLUSIVE} ;
    option.weight = 1;
    type_option.weight = 1;
  }
          atomic_type : coverpoint cov_item.atomic_type {
    bins normal = {svt_axi_transaction::NORMAL};
    bins locked = {svt_axi_transaction::LOCKED};
    ignore_bins atomic_type_axi4 = {svt_axi_transaction::LOCKED}iff((cfg.axi_interface_type == svt_axi_port_configuration::AXI4)||(cfg.locked_access_enable == 0));
    option.weight = 1;
    type_option.weight = 1;
  }
          burst_type : coverpoint cov_item.burst_type iff(cov_burst_type_flag){
    bins fixed_burst = {svt_axi_transaction::FIXED};
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 1;
    type_option.weight = 1;
  }
      axi_burst_size : coverpoint cov_item.burst_size {
    bins burst_size_8bit = {svt_axi_transaction::BURST_SIZE_8BIT};
    bins burst_size_16bit = {svt_axi_transaction::BURST_SIZE_16BIT};
    bins burst_size_32bit = {svt_axi_transaction::BURST_SIZE_32BIT};
    bins burst_size_64bit = {svt_axi_transaction::BURST_SIZE_64BIT};
    bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
    bins burst_size_2048bit = {svt_axi_transaction::BURST_SIZE_2048BIT};
    bins burst_size_4096bit = {svt_axi_transaction::BURST_SIZE_4096BIT};
           option.weight = 1;
    type_option.weight = 1;
  }
              axi_response_type : coverpoint m_response_type {
    bins axi_okay_response = {'b00};
    bins axi_exokay_response = {'b01};
    bins axi_slverr_response = {'b10};
    bins axi_decerr_response = {'b11};
    bins axi_exokay_fail_response = {'b00} iff(cfg.exclusive_access_enable == 1);
    option.weight = 1;
    type_option.weight = 1;
  }
       cache_type : coverpoint cov_item.cache_type {
    bins rd_device_non_bufferable = {0}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_device_bufferable = {1}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_normal_non_cacheable_non_bufferable = {2}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_normal_non_cacheable_bufferable = {3}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_through_no_allocate = {10}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_through_read_allocate = {14}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_through_write_allocate = {10}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_through_read_and_write_allocate = {14}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_back_no_allocate = {11}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_back_read_allocate = {15}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_back_write_allocate = {11}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins rd_write_back_read_and_write_allocate = {15}iff(cov_item.xact_type == svt_axi_transaction::READ);
    bins wr_device_non_bufferable = {0}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_device_bufferable = {1}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_normal_non_cacheable_non_bufferable = {2}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_normal_non_cacheable_bufferable = {3}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_through_no_allocate = {6}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_through_read_allocate = {6}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_through_write_allocate = {14}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_through_read_and_write_allocate = {14}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_back_no_allocate = {7}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_back_read_allocate = {7}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_back_write_allocate = {15}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    bins wr_write_back_read_and_write_allocate = {15}iff(cov_item.xact_type == svt_axi_transaction::WRITE);
    ignore_bins ignore_rsvd = {4,5,8,9,12,13};
   option.weight = 1;
   type_option.weight = 1;
  }
          axi_burst_len : coverpoint cov_item.burst_length {
    bins burst_length[] = {[1:((1<<10)-1)]};
    ignore_bins ignore_unsupported_burst_length_axi4 = {[256+1:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
      axi_address_aligned : coverpoint m_address_aligned {
    wildcard bins axi_8bit_aligned_address ={6'b?????1};
    wildcard bins axi_16bit_aligned_address ={6'b????1?};
    wildcard bins axi_32bit_aligned_address ={6'b???1??};
    wildcard bins axi_64bit_aligned_address ={6'b??1???};
    wildcard bins axi_128bit_aligned_address ={6'b?1????};
    wildcard bins axi_256bit_aligned_address ={6'b1?????};
    option.weight = 1;
    type_option.weight = 1;
  }
         axi_wstrb_beat_0 : coverpoint cov_item.wstrb[0] iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
                  option.weight = 0;
    }
     axi_wstrb_beat_1: coverpoint cov_item.wstrb[1] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h1) {
                option.weight = 0;
    }
     axi_wstrb_beat_2: coverpoint cov_item.wstrb[2] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h2) {
               option.weight = 0;
    }
     axi_wstrb_beat_3: coverpoint cov_item.wstrb[3] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length>= 4'h3) {
               option.weight = 0;
    }
     axi_wstrb_beat_15: coverpoint cov_item.wstrb[15] iff (cov_item.xact_type == svt_axi_transaction::WRITE && cov_item.burst_length == 4'hf) {
               option.weight = 0;
    }
     //crosses the above coverpoints with all_slaves and slaves_excluding
    //register_space
     cache_len_1_all_okay : cross all_slaves, write_xact_type,read_xact_type,cache_type,axi_burst_len,axi_burst_size,axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_len_reduced_all_okay: cross slaves_excluding_register_space,cache_type,write_xact_type,read_xact_type,burst_type,axi_burst_len,axi_response_type {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]};
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_len_reduced_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, burst_type {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h2,[4'h4:4'h6],[4'h8:4'he]};
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h10)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_all_okay_fixed:cross slaves_excluding_register_space,cache_type,axi_burst_size,burst_type,axi_burst_len,axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
          cache_all_slverr_fixed:cross slaves_excluding_register_space, cache_type, axi_burst_size, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
          cache_all_okay_fixed_unaligned:cross slaves_excluding_register_space, cache_type, axi_address_aligned, axi_burst_size, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
      cache_ignore_resp_fixed_unaligned:cross all_slaves, cache_type, axi_address_aligned, axi_burst_size, axi_burst_len, burst_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins Ignore_invalid_fixed = binsof(burst_type.fixed_burst) && binsof(axi_burst_len) intersect {[17:((1<<10))]};
    option.weight = 1;
    type_option.weight = 1;
  }
       master_to_slave_all_okay: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_burst_size, axi_response_type,burst_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, axi_burst_size, burst_type {
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256? 5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_decerr_len_1: cross slaves_excluding_register_space, write_xact_type,read_xact_type, cache_type, axi_burst_len, axi_burst_size, axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_once_decerr = ! binsof (axi_response_type.axi_decerr_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_slverr_len_1: cross slaves_excluding_register_space, cache_type, axi_burst_len, axi_burst_size, axi_response_type {
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ignore_resp_except_once_slverr = ! binsof (axi_response_type.axi_slverr_response);
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_decerr: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type {
    ignore_bins axi_ignore_resp_except_once_decerr = ! binsof (axi_response_type.axi_decerr_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64? 4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128? 5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_slverr: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type {
    ignore_bins axi_ignore_resp_except_once_slverr = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
   }
              master_to_all_slave_ignore_response: cross all_slaves, write_xact_type,read_xact_type, axi_burst_len, burst_type {
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len = (binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
      cross_xact_type_len_1_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_2_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_1 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_for_beat2 = binsof (axi_burst_len) intersect {4'h1};
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_3_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_2 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_len2_for_beat3 = binsof (axi_burst_len) intersect {4'h1,4'h2};
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_xact_type_len_4_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_3 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_len1_len2_len3_for_beat4 = binsof (axi_burst_len) intersect {4'h1,4'h2,4'h3};
    option.weight = 1;
    type_option.weight = 1;
  }
            cross_xact_type_len_16_wstrb: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_len, axi_response_type, burst_type, axi_wstrb_beat_15 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_write_wrap_invalid_len =(binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_incr_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.incr_burst);
    ignore_bins axi_read_wrap_ignore = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst);
    ignore_bins axi_ignore_all_len_except_len16_for_beat16 = binsof (axi_burst_len) intersect {[4'h1:4'hf]};
    option.weight = 1;
    type_option.weight = 1;
  }
            cross_aligned_unaligned_addr_asize: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_size, axi_address_aligned, axi_burst_len, burst_type, axi_response_type {
    ignore_bins axi_ignore_resp_except_all_okay = ! binsof (axi_response_type.axi_okay_response);
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h3,[4'h5:4'h7],[4'h9:4'hf]};
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)} ;
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
           cross_aligned_unaligned_addr_asize_ignore_resp: cross slaves_excluding_register_space, write_xact_type,read_xact_type, axi_burst_size, axi_address_aligned, burst_type, axi_burst_len {
    ignore_bins axi_ignored_len = binsof (axi_burst_len) intersect {4'h2,[4'h4:4'h6],[4'h8:4'he]};
    ignore_bins axi_size_less_than_64bit_len_1_to_16 = (binsof (axi_burst_size) intersect {[3'h0:3'h2]}) && (binsof (axi_burst_len) intersect{[4'h1:5'h10]});
    ignore_bins axi_write_wrap_invalid_len = (binsof (write_xact_type.write_xact) && binsof (burst_type.wrap_burst) && !binsof (axi_burst_len) intersect {2,4,8,16});
    ignore_bins axi_read_wrap_invalid_len_dw_64bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==64?4'h2:5'h11)};
    ignore_bins axi_read_wrap_invalid_len_dw_128bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && binsof (axi_burst_len) intersect {(cfg_data_width==128?5'h10:5'h11)};
    ignore_bins axi_read_wrap_invalid_8len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?4'h8:5'h11)});
    ignore_bins axi_read_wrap_invalid_16len_dw_256bit = binsof (read_xact_type.read_xact) && binsof (burst_type.wrap_burst) && (binsof (axi_burst_len) intersect {(cfg_data_width==256?5'h10:5'h11)});
    option.weight = 1;
    type_option.weight = 1;
  }
           master_to_slave_x_wr_okay_addr_align: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay = ! binsof (axi_response_type.axi_exokay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_x_wr_fail_addr_align: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay_fail = ! binsof (axi_response_type.axi_exokay_fail_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
         master_to_slave_x_wr_decerr: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_decerr = ! binsof (axi_response_type.axi_decerr_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
      master_to_slave_x_wr_slverr: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_burst_size, axi_address_aligned, axi_response_type iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_slverr = ! binsof (axi_response_type.axi_slverr_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_write_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
          master_to_slave_x_wr_okay_wstrb: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_response_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay = ! binsof (axi_response_type.axi_exokay_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_read_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
             master_to_slave_x_wr_fail_wstrb: cross slaves_excluding_register_space, axi_ex_xact_type, cache_type, write_xact_type,read_xact_type, burst_type, axi_burst_len, axi_response_type, axi_wstrb_beat_0 iff (cov_item.xact_type == svt_axi_transaction::WRITE) {
    ignore_bins axi_ignore_resp_except_exokay_fail = ! binsof (axi_response_type.axi_exokay_fail_response);
    ignore_bins axi_ignore_len_greater_than_1 = ! binsof (axi_burst_len) intersect {4'h1};
    ignore_bins axi_ex_read_ignore = (binsof (axi_ex_xact_type.exclusive_type) && binsof (write_xact_type.write_xact) && (binsof (burst_type) intersect {svt_axi_transaction::WRAP,svt_axi_transaction::INCR}));
    option.weight = 1;
    type_option.weight = 1;
  }
         option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_rchunk_xact_type_rchunkstrb_rchunknum_length

This covergroup captures attributes for read channel such as chunken,chunkv,chunk_burst_type, chunk_burst_size,chunk_length,chunkstrobe and chunknum.

Covergroup: trans_cross_rchunk_xact_type_rchunkstrb_rchunknum_length

It is constructed & sampled when interface type can be AXI5 or ACE5_LITE.

Coverpoints:

archunken: Captures archunken values
rchunkv: Captures rchunkv values
chunk_burst_type: Captures burst transaction type
chunk_burst_size: Captures burst size transaction type
chunk_length: Captures chunk_length
rchunkstrb: Captures rchunkstrb values
rchunknum: Captures rchunknum values
rchunkstrb_pattern: Captures rchunkstrb_pattern values
coherent_xact_type: Captures coherent_xact_type values
read_xact_type: Captures xact_type READ value
data_width: Captures data_width values
chunk_burst_length: Captures burst_length values

Cross coverpoints:

rdata_chunk_data_width_burst_size_burst_length: Crosses cover points chunk_burst_size, burst_length, data_width
rdata_chunk_data_width_burst_size: Crosses cover points chunk_burst_size, data_width
rdata_chunk_burst_type_burst_size: Crosses cover points chunk_burst_type, chunk_burst_size
rdata_chunk_chunk_strb_pattern_burst_type_burst_size: Crosses cover point chunk_burst_type, chunk_burst_size, rchunkstrb_pattern
rdata_chunk_archunken_read_xact_type: Crosses cover point read_xact_type, archunken
rdata_chunk_archunken_coherent_xact_type: Crosses cover point coherent_xact_type, archunken
rdata_chunk_rchunkstrb_burst_type_burst_size_xact_type: Crosses cover point rchunkstrb, chunk_burst_type, chunk_burst_size, read_xact_type
rdata_chunk_rchunknum_burst_type_burst_size_xact_type: Crosses cover point rchunknum, chunk_burst_type, chunk_burst_size, read_xact_type
rdata_chunk_rchunkstrb_burst_type_burst_size_coh_xact_type: Crosses cover point rchunkstrb, chunk_burst_type, chunk_burst_size, coherent_xact_type
rdata_chunk_rchunknum_burst_type_burst_size_coh_xact_type: Crosses cover point rchunknum, chunk_burst_type, chunk_burst_size, coherent_xact_type

covergroup trans_cross_rchunk_xact_type_rchunkstrb_rchunknum_length;
     chunk_burst_type : coverpoint cov_item.burst_type iff(cov_chunk_burst_type_flag && cov_item.archunken
                                                        ){
    bins incr_burst = {svt_axi_transaction::INCR};
    bins wrap_burst = {svt_axi_transaction::WRAP};
    option.weight = 0;
    type_option.weight = 0;
  }
    chunk_burst_size : coverpoint cov_item.burst_size iff(cov_chunk_burst_size_flag && cov_item.archunken){
      bins burst_size_128bit = {svt_axi_transaction::BURST_SIZE_128BIT};
    bins burst_size_256bit = {svt_axi_transaction::BURST_SIZE_256BIT};
    bins burst_size_512bit = {svt_axi_transaction::BURST_SIZE_512BIT};
    bins burst_size_1024bit = {svt_axi_transaction::BURST_SIZE_1024BIT};
      option.weight = 0;
    type_option.weight = 0;
  }
    chunk_length : coverpoint cov_item.chunk_length iff(cov_chunk_length_flag && cov_item.archunken
                                                        ){
    bins chunk_length[10] = {[1:((1<<8)-1)]};
    option.weight = 0;
    type_option.weight = 0;
  }
    rchunkstrb : coverpoint cov_rchunkstrb iff(cov_chunkstrb_flag && cov_item.archunken
                                                ){
      bins rchunkstrb[10] = {[1:255]};
    wildcard bins rchunkstrb_bit_position_1 = {'b0000_0001};
    wildcard bins rchunkstrb_bit_position_2 = {'b0000_0010};
    wildcard bins rchunkstrb_bit_position_4 = {'b0000_0100};
    wildcard bins rchunkstrb_bit_position_8 = {'b0000_1000};
    wildcard bins rchunkstrb_bit_position_16 = {'b0001_0000};
    wildcard bins rchunkstrb_bit_position_32 = {'b0010_0000};
    wildcard bins rchunkstrb_bit_position_64 = {'b0100_0000};
    wildcard bins rchunkstrb_bit_position_128 = {'b1000_0000};
    bins rchunkstrb_all_8bit_ones = {8'b1111_1111};
      option.weight = 0;
    type_option.weight = 0;
  }
    rchunknum : coverpoint cov_rchunknum iff(cov_chunknum_flag && cov_item.archunken
                                              ){
      bins rchunknum_val_0 = { [8'h0 : 8'h1F] };
    bins rchunknum_val_1 = { [8'h20 : 8'h3F] };
    bins rchunknum_val_2 = { [8'h40 : 8'h5F] };
    bins rchunknum_val_3 = { [8'h60 : 8'h7F] };
    bins rchunknum_val_4 = { [8'h80 : 8'h9F] };
    bins rchunknum_val_5 = { [8'hA0 : 8'hBF] };
    bins rchunknum_val_6 = { [8'hC0 : 8'hDF] };
    bins rchunknum_val_7 = { [8'hE0 : 8'hFF] };
      option.weight = 0;
    type_option.weight = 0;
  }
    archunken: coverpoint cov_item.archunken iff(cov_archunken_flag){
    bins archunk_0 = {0};
    bins archunk_1 = {1};
    option.weight = 0;
    type_option.weight = 0;
  }
    rchunkstrb_pattern : coverpoint cov_item.rchunkstrb_pattern iff(cov_rchunkstrb_pattern_flag && cov_item.archunken
                                                          ){
    bins all_ones = {svt_axi_transaction::RCHUNKSTRB_ALL_ONES};
    bins walking_ones = {svt_axi_transaction::RCHUNKSTRB_WALKING_ONES};
    bins reverse_ones = {svt_axi_transaction::RCHUNKSTRB_REVERSE_ONES};
    option.weight = 0;
    type_option.weight = 0;
  }
    coherent_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_chunk_coherent_xact_type_flag && (cov_item.xact_type == svt_axi_transaction::COHERENT) && cov_item.archunken
                                                        ){
    bins readnosnoop = {svt_axi_transaction::READNOSNOOP};
    bins readonce = {svt_axi_transaction::READONCE};
    bins readoncecleaninvalid = {svt_axi_transaction::READONCECLEANINVALID};
    bins readoncemakeinvalid = {svt_axi_transaction::READONCEMAKEINVALID};
    option.weight = 0;
    type_option.weight = 0;
  }
    data_width: coverpoint cfg_data_width iff(cov_data_width_flag){
      bins data_width_128 = {128};
    bins data_width_256 = {256};
    bins data_width_512 = {512};
    bins data_width_1024 = {1024};
      option.weight = 0;
    type_option.weight = 0;
  }
    burst_length : coverpoint cov_item.burst_length iff(cov_burst_length_flag){
    bins burst_length_1 = {1};
    bins burst_length[10] = {[2:255]};
    option.weight = 0;
    type_option.weight = 0;
  }
    read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
    rdata_chunk_data_width_burst_size_burst_length: cross chunk_burst_size, burst_length, data_width {
          ignore_bins Ignore_invalid_data_width_128_burst_size_gt128 = binsof(data_width) intersect {128} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_256BIT, svt_axi_transaction::BURST_SIZE_512BIT, svt_axi_transaction::BURST_SIZE_1024BIT};
  ignore_bins Ignore_invalid_data_width_256_burst_size_gt256 = binsof(data_width) intersect {256} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_512BIT, svt_axi_transaction::BURST_SIZE_1024BIT};
  ignore_bins Ignore_invalid_data_width_512_burst_size_gt512 = binsof(data_width) intersect {512} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_1024BIT};
  ignore_bins Ignore_invalid_data_width_256_burst_size_lt256 = binsof(data_width) intersect {256} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_128BIT} && binsof(burst_length) intersect {[2:256]};
  ignore_bins Ignore_invalid_data_width_512_burst_size_lt512 = binsof(data_width) intersect {512} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_128BIT, svt_axi_transaction::BURST_SIZE_256BIT} && binsof(burst_length) intersect {[2:256]};
  ignore_bins Ignore_invalid_data_width_1024_burst_size_lt1024 = binsof(data_width) intersect {1024} && binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_128BIT, svt_axi_transaction::BURST_SIZE_256BIT, svt_axi_transaction::BURST_SIZE_512BIT} && binsof(burst_length) intersect {[2:256]};
  ignore_bins Ignore_invalid_burst_length_burst_size_1024 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_1024BIT} && binsof(burst_length) intersect {[32:256]};
      option.weight = 1;
   }
   rdata_chunk_data_width_burst_size: cross chunk_burst_size, data_width {
    option.weight = 1;
   }
   rdata_chunk_burst_type_burst_size: cross chunk_burst_type, chunk_burst_size {
    option.weight = 1;
   }
   rdata_chunk_chunk_strb_pattern_burst_type_burst_size: cross chunk_burst_type, chunk_burst_size, rchunkstrb_pattern {
    option.weight = 1;
   }
   rdata_chunk_rchunkstrb_burst_type_burst_size_xact_type: cross rchunkstrb, chunk_burst_type, chunk_burst_size, read_xact_type {
          ignore_bins Ignore_invalid_chunk_strb_128 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_128BIT} && binsof(rchunkstrb) intersect {[2:255]};
  ignore_bins Ignore_invalid_chunk_strb_256 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_256BIT} && binsof(rchunkstrb) intersect {[4:255]};
  ignore_bins Ignore_invalid_chunk_strb_512 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_512BIT} && binsof(rchunkstrb) intersect {[16:255]};
      option.weight = 1;
   }
   rdata_chunk_rchunknum_burst_type_burst_size_xact_type: cross rchunknum, chunk_burst_type, chunk_burst_size, read_xact_type {
          ignore_bins Ignore_invalid_chunk_num_256 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_256BIT} && binsof(rchunknum) intersect {[128:255]};
  ignore_bins Ignore_invalid_chunk_num_512 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_512BIT} && binsof(rchunknum) intersect {[64:255]};
  ignore_bins Ignore_invalid_chunk_num_1024 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_1024BIT} && binsof(rchunknum) intersect {[32:255]};
      option.weight = 1;
   }
   rdata_chunk_rchunkstrb_burst_type_burst_size_coh_xact_type: cross rchunkstrb, chunk_burst_type, chunk_burst_size, coherent_xact_type {
          ignore_bins Ignore_invalid_chunk_strb_128 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_128BIT} && binsof(rchunkstrb) intersect {[2:255]};
  ignore_bins Ignore_invalid_chunk_strb_256 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_256BIT} && binsof(rchunkstrb) intersect {[4:255]};
  ignore_bins Ignore_invalid_chunk_strb_512 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_512BIT} && binsof(rchunkstrb) intersect {[16:255]};
      option.weight = 1;
   }
   rdata_chunk_rchunknum_burst_type_burst_size_coh_xact_type: cross rchunknum, chunk_burst_type, chunk_burst_size, coherent_xact_type {
          ignore_bins Ignore_invalid_chunk_num_256 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_256BIT} && binsof(rchunknum) intersect {[128:255]};
  ignore_bins Ignore_invalid_chunk_num_512 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_512BIT} && binsof(rchunknum) intersect {[64:255]};
  ignore_bins Ignore_invalid_chunk_num_1024 = binsof(chunk_burst_size) intersect {svt_axi_transaction::BURST_SIZE_1024BIT} && binsof(rchunknum) intersect {[32:255]};
      option.weight = 1;
   }
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_read_xact_type_armmusecsid_armmusid

This covergroup captures attributes for read transaction type,stream_id and sec_or_non_sec_stream. Covergroup: trans_cross_read_xact_type_awmmusecsid_awmmusid

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

read_xact_type: Captures write transaction type
stream_id: Captures stream id
sec_or_non_sec_stream: Captures sec_or_non_sec_stream

Cross coverpoints:

read_xact_type_armmusecsid_armmusid: Crosses cover points read_xact_type,stream_id and sec_or_non_sec_stream

covergroup trans_cross_read_xact_type_armmusecsid_armmusid;
      stream_id : coverpoint cov_item.stream_id iff(cov_stream_id_flag){
    bins stream_id_range_min = {0};
       bins stream_id_range_mid = {[1:(64'd2**(32)-2)]};
     bins stream_id_range_max = {((64'd2**(32))-1)};
      option.weight = 0;
    type_option.weight = 0;
}
     sec_or_non_sec_stream : coverpoint cov_item.secure_or_non_secure_stream iff(cov_secure_or_non_secure_stream_flag){
   bins secure_stream = {1};
   bins non_secure_stream = {0};
   option.weight = 0;
   type_option.weight = 0;
}
     read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
    read_xact_type_armmusecsid_armmusid : cross read_xact_type,stream_id,sec_or_non_sec_stream{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_read_xact_type_armmussidv_armmussid

This covergroup captures attributes for read transaction type sub_stream_id_valid and sub_stream_id. Covergroup: trans_cross_read_xact_type_armmusecsid_armmusid

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

read_xact_type: Captures write transaction type
sub_stream_id valid: Captures sub_stream id valid
sub_stream_id: Captures sub stream id

Cross coverpoints:

read_xact_type_awmmusecsidv_awmmusid: Crosses cover points read_xact_type,sub_stream_id and sub_stream_id_valid

covergroup trans_cross_read_xact_type_armmussidv_armmussid;
      read_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins read_xact = {svt_axi_transaction::READ};
    option.weight = 0;
    type_option.weight = 0;
  }
     sub_stream_id_valid : coverpoint cov_item.sub_stream_id_valid iff(cov_sub_stream_id_valid_flag){
   bins sub_stream_id_valid = {1};
   bins sub_stream_id_invalid = {0};
   option.weight = 0;
   type_option.weight = 0;
}
     sub_stream_id : coverpoint cov_item.sub_stream_id iff(cov_sub_stream_id_flag){
     bins sub_stream_id_range_min = {0};
       bins sub_stream_id_range_mid = {[1:(64'd2**(20)-2)]};
     bins sub_stream_id_range_max = {((64'd2**(20))-1)};
     option.weight = 0;
   type_option.weight = 0;
}
    read_xact_type_armmussidv_armmussid : cross read_xact_type,sub_stream_id,sub_stream_id_valid{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_stash_xact_type_stash_lpid_stashlpid_valid

Covergroup: trans_cross_stash_xact_type_stash_lpid_stashlpid_valid

It is constructed & sampled only when svt_axi_port_configuration :: axi_interface_type is set to ACE_LITE,svt_axi_port_configuration :: ace_version is set to ACE_VERSION_2_0 and svt_axi_port_configuration :: cache_stashing_enable set to 1.

Coverpoints:

coherent_stash_xact_type: Captures coherent stash transaction type
stash_lpid: Captures stash_lpid
stash_lpid_valid: Captures whether stash_lpid is valid or not

Cross coverpoints:

coherent_stash_xact_type_stash_lpid_stash_lpid_valid: Crosses cover points coherent_stash_xact_type, stash_lpid and stash_lpid_valid

covergroup trans_cross_stash_xact_type_stash_lpid_stashlpid_valid;
     coherent_stash_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_stash_xact_type_flag){
    bins coherent_writeuniqueptlstash_xact = {svt_axi_transaction::WRITEUNIQUEPTLSTASH};
    bins coherent_writeuniquefullstash_xact = {svt_axi_transaction::WRITEUNIQUEFULLSTASH};
    bins coherent_stashonceshared_xact = {svt_axi_transaction::STASHONCESHARED};
    bins coherent_stashonceunique_xact = {svt_axi_transaction::STASHONCEUNIQUE};
    bins coherent_stashtranslation_xact = {svt_axi_transaction::STASHTRANSLATION};
    option.weight = 0;
    type_option.weight = 0;
}
    stash_lpid_valid : coverpoint cov_item.stash_lpid_valid iff(cov_stash_lpid_valid_flag){
   bins stash_lpid_valid = {1};
   bins stash_lpid_invalid = {0};
   option.weight =0;
   type_option.weight =0;
}
    stash_lpid : coverpoint cov_item.stash_lpid iff(cov_stash_lpid_flag){
       bins stash_lpid_range_min = {0};
       bins stash_lpid_range_mid = {[1:(64'd2**(5)-2)]};
     bins stash_lpid_range_max = {((64'd2**(5))-1)};
    option.weight = 0;
  type_option.weight = 0;
}
   coherent_stash_xact_type_stash_lpid_stash_lpid_valid : cross coherent_stash_xact_type,stash_lpid,stash_lpid_valid{
    option.weight = 1;
   }
   option.per_instance = 1;
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_stash_xact_type_stash_nid_stashnid_valid

Covergroup: trans_cross_stash_xact_type_stash_nid_stashnid_valid

Coverpoints:

coherent_stash_xact_type: Captures coherent stash transaction type
stash_nid: Captures stash_nid
stash_nid_valid: Captures whether stash_nid is valid or not

Cross coverpoints:

coherent_stash_xact_type_stash_nid_stash_nid_valid: Crosses cover points coherent_stash_xact_type, stash_nid and stash_nid_valid

covergroup trans_cross_stash_xact_type_stash_nid_stashnid_valid;
     coherent_stash_xact_type : coverpoint cov_item.coherent_xact_type iff(cov_coherent_stash_xact_type_flag){
    bins coherent_writeuniqueptlstash_xact = {svt_axi_transaction::WRITEUNIQUEPTLSTASH};
    bins coherent_writeuniquefullstash_xact = {svt_axi_transaction::WRITEUNIQUEFULLSTASH};
    bins coherent_stashonceshared_xact = {svt_axi_transaction::STASHONCESHARED};
    bins coherent_stashonceunique_xact = {svt_axi_transaction::STASHONCEUNIQUE};
    bins coherent_stashtranslation_xact = {svt_axi_transaction::STASHTRANSLATION};
    option.weight = 0;
    type_option.weight = 0;
}
    stash_nid_valid : coverpoint cov_item.stash_nid_valid iff(cov_stash_nid_valid_flag){
   bins stash_nid_valid = {1};
   bins stash_nid_invalid = {0};
   option.weight = 0;
   type_option.weight = 0;
}
    stash_nid : coverpoint cov_item.stash_nid iff(cov_stash_nid_flag){
      bins stash_nid_range_min = {0};
       bins stash_nid_range_mid = {[1:(64'd2**(11)-2)]};
     bins stash_nid_range_max = {((64'd2**(11))-1)};
      option.weight = 0;
    type_option.weight = 0;
}
   coherent_stash_xact_type_stash_nid_stash_nid_valid : cross coherent_stash_xact_type,stash_nid,stash_nid_valid{
    option.weight = 1;
   }
   option.per_instance = 1;
   endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_stream_xact_type_tid_tdest

Covergroup: trans_cross_stream_xact_type_tid_tdest

This Covergroup captures stream xact_type, stream tid and stream tdest. It is constructed when interface_type is AXI4_STREAM and trans_cross_stream_xact_type_tid_tdest_enable set to 1.

Coverpoints:

stream_xact_type: Captures the type of stream
stream_tid: Captures the value of TID
stream_tdest: Captures the value of TDEST

Cross coverpoints:

trans_cross_stream_xact_type_tid_tdest: Crosses cover points stream_xact_type, stream_tid and stream_tdest
trans_cross_stream_xact_type_tid: Crosses coverpoints stream_xact_type and stream_tid
trans_cross_stream_xact_type_tdest: Crosses coverpoints stream_xact_type and stream_tdest

covergroup trans_cross_stream_xact_type_tid_tdest @ ( cov_stream_sample_event ) ;
      stream_xact_type : coverpoint cov_stream_xact_type iff(cov_stream_xact_type_flag){
    bins byte_stream = {svt_axi_transaction::BYTE_STREAM};
    bins continuous_aligned_stream = {svt_axi_transaction::CONTINUOUS_ALIGNED_STREAM};
    bins continuous_unaligned_stream = {svt_axi_transaction::CONTINUOUS_UNALIGNED_STREAM};
    bins sparse_stream = {svt_axi_transaction::SPARSE_STREAM};
    bins user_stream = {svt_axi_transaction::USER_STREAM};
    ignore_bins ignore_byte_stream = {svt_axi_transaction::BYTE_STREAM} iff(cfg_byte_stream_enable==0);
    ignore_bins ignore_continuous_aligned_stream = {svt_axi_transaction::CONTINUOUS_ALIGNED_STREAM} iff(cfg_continuous_aligned_stream_enable==0);
    ignore_bins ignore_continuous_unaligned_stream = {svt_axi_transaction::CONTINUOUS_UNALIGNED_STREAM} iff(cfg_continuous_unaligned_stream_enable==0);
    ignore_bins ignore_sparse_stream = {svt_axi_transaction::SPARSE_STREAM} iff(cfg_sparse_stream_enable==0);
    ignore_bins ignore_user_stream = {svt_axi_transaction::USER_STREAM} iff(cfg_user_stream_enable==0);
    option.weight = 0;
    type_option.weight = 0;
  }
     stream_tid : coverpoint cov_item.tid iff (cov_stream_tid_flag) {
      bins tid_within_range[] = {[0:((1<<cfg_tid_width)-1)]};
      ignore_bins ignore_tid_if_disabled = {[0:$]} iff (cfg_tid_enable==0);
    option.weight = 0;
    type_option.weight = 0;
  }
     stream_tdest : coverpoint cov_item.tdest iff (cov_stream_tdest_flag) {
      bins tdest_within_range[] = {[0:((1<<cfg_tdest_width)-1)]};
      ignore_bins ignore_tdest_if_disabled = {[0:$]} iff (cfg_tdest_enable==0);
    option.weight = 0;
    type_option.weight = 0;
}
    trans_cross_stream_xact_type_tid: cross stream_xact_type, stream_tid {
       option.weight = 1;
     }
     trans_cross_stream_xact_type_tdest: cross stream_xact_type, stream_tdest {
       option.weight = 1;
     }
     trans_cross_stream_xact_type_tid_tdest: cross stream_xact_type, stream_tid, stream_tdest {
      option.weight = 1;
     }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_write_xact_type_awmmusecsid_awmmusid

This covergroup captures attributes for stream_id,sec or non_sec_stream and transaction type. Covergroup: trans_cross_write_xact_type_awmmusecsid_awmmusid

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

write_xact_type: Captures write transaction type
sec or non_sec_stream: Captures secure or non_secure stream
stream_id: Captures stream id

Cross coverpoints:

write_xact_type_awmmusecsid_awmmusid: Crosses cover points write_xact_type,stream_id and sec_or_non_sec_stream

covergroup trans_cross_write_xact_type_awmmusecsid_awmmusid;
      stream_id : coverpoint cov_item.stream_id iff(cov_stream_id_flag){
    bins stream_id_range_min = {0};
       bins stream_id_range_mid = {[1:(64'd2**(32)-2)]};
     bins stream_id_range_max = {((64'd2**(32))-1)};
      option.weight = 0;
    type_option.weight = 0;
}
     sec_or_non_sec_stream : coverpoint cov_item.secure_or_non_secure_stream iff(cov_secure_or_non_secure_stream_flag){
   bins secure_stream = {1};
   bins non_secure_stream = {0};
   option.weight = 0;
   type_option.weight = 0;
}
     write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
    write_xact_type_awmmusecsid_awmmusid : cross write_xact_type,stream_id,sec_or_non_sec_stream{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_cross_write_xact_type_awmmussidv_awmmussid

This covergroup captures attributes for write transaction type sub_stream_id_valid and sub_stream_id. Covergroup: trans_cross_write_xact_type_awmmusecsid_awmmusid

It is constructed & sampled when interface type can be ACE_LITE , AXI4 & ACE_VERSION_2_0

Coverpoints:

write_xact_type: Captures write transaction type
sub_stream_id valid: Captures sub_stream id valid
sub_stream_id: Captures sub stream id

Cross coverpoints:

write_xact_type_awmmusecsidv_awmmusid: Crosses cover points write_xact_type,sub_stream_id and sub_stream_id_valid

covergroup trans_cross_write_xact_type_awmmussidv_awmmussid;
      write_xact_type : coverpoint cov_xact_rd_wr_type iff(cov_xact_type_flag){
    bins write_xact = {svt_axi_transaction::WRITE};
    option.weight = 0;
    type_option.weight = 0;
  }
     sub_stream_id_valid : coverpoint cov_item.sub_stream_id_valid iff(cov_sub_stream_id_valid_flag){
   bins sub_stream_id_valid = {1};
   bins sub_stream_id_invalid = {0};
   option.weight = 0;
   type_option.weight = 0;
}
     sub_stream_id : coverpoint cov_item.sub_stream_id iff(cov_sub_stream_id_flag){
     bins sub_stream_id_range_min = {0};
       bins sub_stream_id_range_mid = {[1:(64'd2**(20)-2)]};
     bins sub_stream_id_range_max = {((64'd2**(20))-1)};
     option.weight = 0;
   type_option.weight = 0;
}
     write_xact_type_awmmussidv_awmmussid : cross write_xact_type,sub_stream_id,sub_stream_id_valid{
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_barrier_response_with_outstanding_xacts

Covergroup: trans_master_ace_barrier_response_with_outstanding_xacts

It is constructed and sampled when system_ace_barrier_response_with_outstanding_xacts_enable ,barrier_enable and system_monitor_enable set to 1.

system_ace_barrier_response_with_outstanding_xacts_enable Coverpoints:

ace_completed_barrier_type: This is covered when there are outstanding transactions in the queue of a master when the response to a barrier is received. There are multiple ways in which an interconnect can handle barriers. Some interconnects may send response to a barrier only after all outstanding transactions are complete. Others may forward the barrier downstream and wait for the response of the downstream barrier before responding to the original barrier. In such a case there could be outstanding transactions in the queue of the master when a barrier response is received. This coverpoint covers the latter behaviour.
One or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.3

covergroup trans_master_ace_barrier_response_with_outstanding_xacts;
     ace_completed_barrier_type: coverpoint completed_barrier_xact.barrier_type {
      bins outstanding_xacts_during_memory_barrier = {svt_axi_transaction::MEMORY_BARRIER};
      bins outstanding_xacts_during_sync_barrier = {svt_axi_transaction::SYNC_BARRIER};
      ignore_bins ignore_barrier_type = {svt_axi_transaction::NORMAL_ACCESS_RESPECT_BARRIER,svt_axi_transaction::NORMAL_ACCESS_IGNORE_BARRIER};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_coherent_and_ace_snoop_response_association

Covergroup: trans_master_ace_coherent_and_ace_snoop_response_association

Covergroup for all coherent transactions generated from ACE master and the correponding Snoop transactions on ACE-Masters and snoop response from ACE-Masters for these snoop transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there are two ACE master s in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_coherent_and_ace_snoop_response_association_enable to 1.

Coverpoints:

coh_xact_from_ace: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE master resulted in this snoop transaction and snoop response and subsequently hit bins of coverpoint cmds_from_ace. System Monitor provides this information to Port Monitor.
snoop_xact_on_ace_master: This coverpoint has bins corresponding to each of the valid snoop transaction type on ACE master
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace, snoop_xact_on_ace_master,snp_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_coherent_and_ace_snoop_response_association;
       coh_xact_from_ace: coverpoint ace_coh_xact_type {
    bins coherent_readonce_xact = {svt_axi_transaction::READONCE};
    bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
    bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
    bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
    bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
    bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
    bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
    bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
    bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
    bins writeunique_coherent = {svt_axi_transaction::WRITEUNIQUE};
    bins writelineunique_coherent = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_from_ace: coverpoint snoop_resp_from_ace_master[3:0] {
    bins cresp_0000 = {4'b0000};
    bins cresp_1000 = {4'b1000};
    bins cresp_0001 = {4'b0001};
    bins cresp_1001 = {4'b1001};
    bins cresp_0101 = {4'b0101};
    bins cresp_1101 = {4'b1101};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_wu : coverpoint snoop_resp_from_ace_master[4] {
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_init_cache_state: coverpoint ace_master_init_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_final_cache_state: coverpoint ace_master_final_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_xact_on_ace_master: coverpoint ace_master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
    bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
    bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
    bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
    coh_xact_ace_snp_resp_ace_init_final_cache_state : cross coh_xact_from_ace, snoop_xact_on_ace_master,snoop_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state, ace_final_cache_state {
           ignore_bins ignore_coherent_snoop_not_possible_combinations = ((binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::MAKEINVALID} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::MAKEINVALID}) ||
                                                                (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::READONCE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::READONCE}) ||
                                                                  (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANSHARED}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::CLEANINVALID} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANINVALID}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::WRITEUNIQUE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANINVALID}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::WRITELINEUNIQUE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::MAKEINVALID}) ||
                                                                (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::READSHARED} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::READSHARED}) ||
                                                                (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::READCLEAN} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::READCLEAN}) ||
                                                                  (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::READNOTSHAREDDIRTY} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::READNOTSHAREDDIRTY}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::READUNIQUE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::READUNIQUE}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::MAKEUNIQUE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::MAKEINVALID}) ||
                                                                   (binsof(coh_xact_from_ace) intersect {
                                                                   svt_axi_transaction::CLEANUNIQUE} &&
                                                                 !binsof(snoop_xact_on_ace_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANINVALID}));
    ignore_bins ignore_invalid_crresp_ud_sc_sd = binsof(coh_xact_from_ace) intersect {
                                                   svt_axi_transaction::MAKEINVALID ,svt_axi_transaction::WRITELINEUNIQUE} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000 };
   ignore_bins ignore_invalid_makeinvalid_crresp_ud_sc_sd = binsof(snoop_xact_on_ace_master) intersect {
                                                   svt_axi_snoop_transaction::MAKEINVALID} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000};
  ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coh_xact_from_ace) intersect {
                                                   svt_axi_transaction::WRITEUNIQUE , svt_axi_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000,4'b0101 };
  ignore_bins Ignore_invalid_cleaninvalid_rresp_ud_sc_sd = binsof(snoop_xact_on_ace_master) intersect {
                                                   svt_axi_snoop_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000,4'b0101 };
    ignore_bins ignore_invalid_crresp_cleanshared = binsof(coh_xact_from_ace) intersect {
                                                       svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST} &&
                                                       binsof(snoop_crresp_from_ace) intersect {
                                                       4'b1001,4'b0001};
    ignore_bins Ignore_invalid_crresp_readonce = binsof(coh_xact_from_ace) intersect {
                                                     svt_axi_transaction::READONCE} &&
                                                     binsof(snoop_crresp_from_ace) intersect {
                                                      4'b1000};
  ignore_bins ignore_data_transfer_start_cache_state = binsof(snoop_crresp_from_ace) intersect {4'b0001,4'b0101,4'b1101,4'b1001} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_is_shared_end_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b1000,4'b1101,4'b1001} && binsof(ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_pass_dirty_start_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b0101,4'b1101} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
    ignore_bins ignore_cleanshared_crresp = binsof(coh_xact_from_ace) intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST,svt_axi_transaction::READONCE} && binsof(snoop_crresp_from_ace) intersect {4'b1000,4'b1001,4'b1101} && binsof (ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
    ignore_bins ignore_wasunique = !binsof(ace_init_cache_state)intersect {svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::UNIQUEDIRTY} && binsof (snoop_crresp_wu) intersect {1} ;
  ignore_bins Ignore_readonce_states = (((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                                ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                                (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                                ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                               ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::SHAREDCLEAN}))) ;
    ignore_bins Ignore_cleanshared_states = ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN}));
      ignore_bins Ignore_readshared_readclean_states = ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READSHARED,svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READSHARED,svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                               ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::READSHARED,svt_axi_transaction::READCLEAN,svt_axi_transaction::READNOTSHAREDDIRTY}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::SHAREDDIRTY}));
  ignore_bins Ignore_cleaninvalid_states_ignore_readunique_states = ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::CLEANINVALID,svt_axi_transaction::READUNIQUE}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                                   ((binsof(snoop_xact_on_ace_master) intersect
                                                    {svt_axi_snoop_transaction::CLEANINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
  ignore_bins Ignore_makeinvalid_states = ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::MAKEINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                           ((binsof(snoop_xact_on_ace_master) intersect
                                                    {svt_axi_snoop_transaction::MAKEINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
  ignore_bins Ignore_writeuniqueorline_states = ((binsof(coh_xact_from_ace) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                   (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
    ignore_bins ignore_readonce_cleanshared_init_ud_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(ace_init_cache_state) intersect{svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001} || binsof(coh_xact_from_ace)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001};
    ignore_bins ignore_readonce_final_sc_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDCLEAN}&&binsof(snoop_crresp_from_ace) intersect{4'b1101} ;
    ignore_bins ignore_readonce_01_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0101} ;
    ignore_bins ignore_readonce_final_10_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDDIRTY};
  ignore_bins ignore_readonce_final_sc_10_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY};
    ignore_bins ignore_cleanshared_init_sd_ud_state = binsof (coh_xact_from_ace)intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} && !binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
    ignore_bins ignore_cleaninvalid_writeunique_init_state = binsof(snoop_xact_on_ace_master)intersect {svt_axi_snoop_transaction::CLEANINVALID}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY, svt_axi_snoop_transaction::SHAREDDIRTY} && binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001};
ignore_bins ignore_readshared_illegal_combinations_invalid = binsof(snoop_xact_on_ace_master)intersect {svt_axi_snoop_transaction::READSHARED,svt_axi_snoop_transaction::READCLEAN,svt_axi_snoop_transaction::READNOTSHAREDDIRTY}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID} &&binsof(ace_final_cache_state)intersect{svt_axi_snoop_transaction::INVALID} && !binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001};
  ignore_bins ignore_readshared_illegal_combinations_uniqueclean = binsof(snoop_xact_on_ace_master)intersect {svt_axi_snoop_transaction::READSHARED,svt_axi_snoop_transaction::READCLEAN,svt_axi_snoop_transaction::READNOTSHAREDDIRTY}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::SHAREDCLEAN} &&binsof(ace_final_cache_state)intersect{svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN} && !binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001,4'b0101};
ignore_bins ignore_readshared_illegal_combinations_uniquedirty = binsof(snoop_xact_on_ace_master)intersect {svt_axi_snoop_transaction::READSHARED,svt_axi_snoop_transaction::READCLEAN,svt_axi_snoop_transaction::READNOTSHAREDDIRTY}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY} &&binsof(ace_final_cache_state)intersect{svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::SHAREDDIRTY} && binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001};
       option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_coherent_and_snoop_association_recommended_ace

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace

This Covergroup captures scenari when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1.

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_coherent_and_snoop_association_recommended_ace;
      ace_coh_and_snp_association: coverpoint coh_and_snp_association {
      bins readonce_coherent_to_readonce_snoop = {16'h01_00};
      bins readclean_coherent_to_readclean_snoop = {16'h03_02};
      bins readnotshareddirty_coherent_to_readnotshareddirty_snoop = {16'h04_03};
      bins readshared_coherent_to_readshared_snoop = {16'h02_01};
      bins readunique_coherent_to_readunique_snoop = {16'h05_07};
      bins cleanunique_coherent_to_cleaninvalid_snoop = {16'h06_09};
      bins makeunique_coherent_to_makeinvalid_snoop = {16'h07_0d};
      bins cleanshared_coherent_to_cleanshared_snoop = {16'h08_08};
       bins cleansharedpersist_coherent_to_cleanshared_snoop = {16'h10_08};
      bins cleaninvalid_coherent_to_cleaninvalid_snoop = {16'h09_09};
      bins makeinvalid_coherent_to_makeinvalid_snoop = {16'h0a_0d};
      bins writeunique_coherent_to_cleaninvalid_snoop = {16'h0f_09};
      bins writelineunique_coherent_to_makeinvalid_snoop = {16'h10_0d};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_coherent_and_snoop_association_recommended_ace_lite

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_ace_lite

This Covergroup captures scenario when master issues coherant transaction , interconnect recommends snooop based transaction to snooped masters. It is constructed and sampled when interface _type is ACE_LITE .

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_coherent_and_snoop_association_recommended_ace_lite;
      ace_coh_and_snp_association: coverpoint coh_and_snp_association {
      bins readonce_coherent_to_readonce_snoop = {16'h01_00};
      bins cleanshared_coherent_to_cleanshared_snoop = {16'h08_08};
       bins cleansharedpersist_coherent_to_cleanshared_snoop = {16'h10_08};
      bins cleaninvalid_coherent_to_cleaninvalid_snoop = {16'h09_09};
      bins makeinvalid_coherent_to_makeinvalid_snoop = {16'h0a_0d};
      bins writeunique_coherent_to_cleaninvalid_snoop = {16'h0f_09};
      bins writelineunique_coherent_to_makeinvalid_snoop = {16'h10_0d};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace

Covergroup: system_ace_coherent_and_snoop_association_recommended_and_optional_ace

This Covergroup captures optional snoop transactions to snooped masters when coherant transaction is received from initiating master. It is constructed when interface_type is AXI_ACE and system_ace_coherent_and_snoop_association_enable set to 1.

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace;
     ace_coh_and_snp_association: coverpoint coh_and_snp_association {
      bins readonce_coherent_to_readonce_snoop = {16'h01_00};
      bins readonce_coherent_to_readclean_snoop = {16'h01_02};
      bins readonce_coherent_to_readnotshareddirty_snoop = {16'h01_03};
      bins readonce_coherent_to_readshared_snoop = {16'h01_01};
      bins readonce_coherent_to_readunique_snoop = {16'h01_07};
      bins readonce_coherent_to_cleaninvalid_snoop = {16'h01_09};
      bins readonce_coherent_to_cleanshared_snoop = {16'h01_08};
              bins readclean_coherent_to_readclean_snoop = {16'h03_02};
       bins readclean_coherent_to_readnotshareddirty_snoop = {16'h03_03};
      bins readclean_coherent_to_readshared_snoop = {16'h03_01};
      bins readclean_coherent_to_readunique_snoop = {16'h03_07};
      bins readclean_coherent_to_cleaninvalid_snoop = {16'h03_09};
         bins readnotshareddirty_coherent_to_readclean_snoop = {16'h04_02};
      bins readnotshareddirty_coherent_to_readnotshareddirty_snoop = {16'h04_03};
      bins readnotshareddirty_coherent_to_readshared_snoop = {16'h04_01};
      bins readnotshareddirty_coherent_to_readunique_snoop = {16'h04_07};
      bins readnotshareddirty_coherent_to_cleaninvalid_snoop = {16'h04_09};
         bins readshared_coherent_to_readclean_snoop = {16'h02_02};
      bins readshared_coherent_to_readnotshareddirty_snoop = {16'h02_03};
      bins readshared_coherent_to_readshared_snoop = {16'h02_01};
      bins readshared_coherent_to_readunique_snoop = {16'h02_07};
      bins readshared_coherent_to_cleaninvalid_snoop = {16'h02_09};
         bins readunique_coherent_to_readunique_snoop = {16'h05_07};
      bins readunique_coherent_to_cleaninvalid_snoop = {16'h05_09};
         bins cleanunique_coherent_to_readunique_snoop = {16'h06_07};
      bins cleanunique_coherent_to_cleaninvalid_snoop = {16'h06_09};
         bins makeunique_coherent_to_readunique_snoop = {16'h07_07};
      bins makeunique_coherent_to_cleaninvalid_snoop = {16'h07_09};
       bins makeunique_coherent_to_makeinvalid_snoop = {16'h07_0d};
         bins cleanshared_coherent_to_readunique_snoop = {16'h08_07};
      bins cleanshared_coherent_to_cleaninvalid_snoop = {16'h08_09};
      bins cleanshared_coherent_to_cleanshared_snoop = {16'h08_08};
       bins cleansharedpersist_coherent_to_readunique_snoop = {16'h10_07};
      bins cleansharedpersist_coherent_to_cleaninvalid_snoop = {16'h10_09};
      bins cleansharedpersist_coherent_to_cleanshared_snoop = {16'h10_08};
      bins cleaninvalid_coherent_to_readunique_snoop = {16'h09_07};
      bins cleaninvalid_coherent_to_cleaninvalid_snoop = {16'h09_09};
         bins makeinvalid_coherent_to_readunique_snoop = {16'h0a_07};
      bins makeinvalid_coherent_to_cleaninvalid_snoop = {16'h0a_09};
      bins makeinvalid_coherent_to_makeinvalid_snoop = {16'h0a_0d};
         bins writeunique_coherent_to_readunique_snoop = {16'h0f_07};
      bins writeunique_coherent_to_cleaninvalid_snoop = {16'h0f_09};
         bins writelineunique_coherent_to_readunique_snoop = {16'h10_07};
      bins writelineunique_coherent_to_cleaninvalid_snoop = {16'h10_09};
      bins writelineunique_coherent_to_makeinvalid_snoop = {16'h10_0d};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite

Covergroup: trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite

Coverpoints:

ace_coh_and_snp_association: This is covered when the interconnect issues recommended and optional snoop transaction to the snooped masters, in response to the coherent transaction received from the initiating master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_coherent_and_snoop_association_recommended_and_optional_ace_lite;
     ace_coh_and_snp_association: coverpoint coh_and_snp_association {
      bins readonce_coherent_to_readonce_snoop = {16'h01_00};
      bins readonce_coherent_to_readclean_snoop = {16'h01_02};
      bins readonce_coherent_to_readnotshareddirty_snoop = {16'h01_03};
      bins readonce_coherent_to_readshared_snoop = {16'h01_01};
      bins readonce_coherent_to_readunique_snoop = {16'h01_07};
      bins readonce_coherent_to_cleaninvalid_snoop = {16'h01_09};
      bins readonce_coherent_to_cleanshared_snoop = {16'h01_08};
              bins cleanshared_coherent_to_readunique_snoop = {16'h08_07};
      bins cleanshared_coherent_to_cleaninvalid_snoop = {16'h08_09};
      bins cleanshared_coherent_to_cleanshared_snoop = {16'h08_08};
       bins cleansharedpersist_coherent_to_readunique_snoop = {16'h10_07};
      bins cleansharedpersist_coherent_to_cleaninvalid_snoop = {16'h10_09};
      bins cleansharedpersist_coherent_to_cleanshared_snoop = {16'h10_08};
      bins cleaninvalid_coherent_to_readunique_snoop = {16'h09_07};
      bins cleaninvalid_coherent_to_cleaninvalid_snoop = {16'h09_09};
         bins makeinvalid_coherent_to_readunique_snoop = {16'h0a_07};
      bins makeinvalid_coherent_to_cleaninvalid_snoop = {16'h0a_09};
      bins makeinvalid_coherent_to_makeinvalid_snoop = {16'h0a_0d};
         bins writeunique_coherent_to_readunique_snoop = {16'h0f_07};
      bins writeunique_coherent_to_cleaninvalid_snoop = {16'h0f_09};
         bins writelineunique_coherent_to_readunique_snoop = {16'h10_07};
      bins writelineunique_coherent_to_cleaninvalid_snoop = {16'h10_09};
      bins writelineunique_coherent_to_makeinvalid_snoop = {16'h10_0d};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_concurrent_overlapping_coherent_xacts

Covergroup: trans_master_ace_concurrent_overlapping_coherent_xacts

The covergroup trans_master_ace_concurrent_overlapping_coherent_xacts covers coherent transactions initiated from different ACE masters concurrently on the same address. The covergroup needs atlease two ACE masters to be present in the system. It is constructed and sampled when interface_type is AXI_ACE and system_ace_concurrent_overlapping_coherent_xacts_enable set to 1. Coverpoints:

coherent_xact_on_ace_master_port: This coverpoint covers svt_axi_transaction :: coherent_xact_type transaction . All coherent transactions capable of generating snoop are bins of this coverpoint .
coherent_xact_on_other_ace_master_port_in_system : This coverpoint covers svt_axi_transaction :: coherent_xact_type transactions . All coherent transactions capable of generating snoop are bins of this coverpoint .

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613;

covergroup trans_master_ace_concurrent_overlapping_coherent_xacts;
     coherent_xact_on_ace_master_port: coverpoint coherent_xact_on_port1{
      bins coherent_readonce_xact = {svt_axi_transaction::READONCE} ;
      bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
      bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
      bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
      bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
      bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
      bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
      bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
       bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
      bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
      bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
      bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
      option.weight = 1;
    }
         coherent_xact_on_other_ace_master_port_in_system : coverpoint coherent_xact_on_port2{
      bins coherent_readonce_xact = {svt_axi_transaction::READONCE} ;
      bins coherent_readshared_xact = {svt_axi_transaction::READSHARED};
      bins coherent_readclean_xact = {svt_axi_transaction::READCLEAN};
      bins coherent_readnotshareddirty_xact = {svt_axi_transaction::READNOTSHAREDDIRTY};
      bins coherent_readunique_xact = {svt_axi_transaction::READUNIQUE};
      bins coherent_cleanunique_xact = {svt_axi_transaction::CLEANUNIQUE};
      bins coherent_makeunique_xact = {svt_axi_transaction::MAKEUNIQUE};
      bins coherent_cleanshared_xact = {svt_axi_transaction::CLEANSHARED};
       bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins coherent_cleaninvalid_xact = {svt_axi_transaction::CLEANINVALID};
      bins coherent_makeinvalid_xact = {svt_axi_transaction::MAKEINVALID};
      bins coherent_writeunique_xact = {svt_axi_transaction::WRITEUNIQUE};
      bins coherent_writelineunique_xact = {svt_axi_transaction::WRITELINEUNIQUE};
      option.weight = 1;
    }
         ace_concurrent_overlapping: cross coherent_xact_on_ace_master_port ,coherent_xact_on_other_ace_master_port_in_system {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_concurrent_readunique_cleanunique

Covergroup: trans_master_ace_concurrent_readunique_cleanunique

This Covergroup captures scenario for ACE master initiating simultanous ReadUnique or CleanUnique transactions. It is consstructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_concurrent_readunique_cleanunique_enable set to 1.

Coverpoints:

ace_concurrent_readunique_cleanunique: This is covered when multiple ACE masters concurrently(that are simultaneously active) initiate ReadUnique or CleanUnique transactions.
Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

covergroup trans_master_ace_concurrent_readunique_cleanunique;
      ace_concurrent_readunique_cleanunique: coverpoint concurrent_readunique_cleanunique {
      bins readunique_readunique = {16'h05_05};
      bins readunique_cleanunique = {16'h05_09,16'h09_05};
      bins cleanunique_cleannique = {16'h09_09};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_cross_cache_line_dirty_data_write

Covergroup: trans_master_ace_cross_cache_line_dirty_data_write

This is a system-level covergroup which works by enabling sys_cfg field system_which captures dirty data for write cache line. It is constructed and sampled when interface_type is AXI_ACE or ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_cross_cache_line_dirty_data_write_enable set to 1.

Coverpoints:

ace_cross_cache_line_dirty_data_write: This is covered under the following conditions:
- The interconnect may need to snoop multiple cachelines for a WRITEUNIQUE or READONCE transaction because it spans multiple cache lines
- Atleast two of these snoop transactions return dirty data
- The interconnect writes the dirty data of the snoop transactions to slave
  One or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

covergroup trans_master_ace_cross_cache_line_dirty_data_write;
      ace_cross_cache_line_dirty_data_write: coverpoint master_xact_of_ic_dirty_data_write.coherent_xact_type {
      bins readonce_cross_cache_line_dirty_data_write = {svt_axi_transaction::READONCE};
      bins writeunique_cross_cache_line_dirty_data_write = {svt_axi_transaction::WRITEUNIQUE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_dirty_data_write

Covergroup: trans_master_ace_dirty_data_write

This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is AXI_ACE,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1.

Coverpoints:

master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction
Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

covergroup trans_master_ace_dirty_data_write;
     ace_dirty_data_write: coverpoint master_xact_of_ic_dirty_data_write.coherent_xact_type {
      bins readonce_dirty_data_write = {svt_axi_transaction::READONCE};
      bins readclean_dirty_data_write = {svt_axi_transaction::READCLEAN};
      bins readnotshreaddirty_dirty_data_write = {svt_axi_transaction::READNOTSHAREDDIRTY};
      bins cleaninvalid_dirty_data_write = {svt_axi_transaction::CLEANINVALID};
      bins cleanshared_dirty_data_write = {svt_axi_transaction::CLEANSHARED};
       bins cleansharedpersist_dirty_data_write = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins cleanunique_dirty_data_write = {svt_axi_transaction::CLEANUNIQUE};
      bins writeunique_dirty_data_write = {svt_axi_transaction::WRITEUNIQUE};
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_dirty_data_write_one_ace_acelite

Covergroup: trans_master_ace_dirty_data_write_one_ace_acelite

This is a system-level covergroup which works by enabling sys_cfg field system_ace_dirty_data_write_enable. It is constructed and sampled when interface_type is ACE_LITE ,interface_category is AXI_READ_WRITE and system_ace_dirty_data_write_enable set to 1.

Coverpoints:

master_xact_of_ic_dirty_data_write: This is covered when the interconnect issues a write to the slave because dirty data was returned by one of the snoop responses and that dirty data could not be returned to the master that initiated the original transaction
One ACE and one or more ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 13.4

covergroup trans_master_ace_dirty_data_write_one_ace_acelite;
     ace_dirty_data_write: coverpoint master_xact_of_ic_dirty_data_write.coherent_xact_type {
      bins readonce_dirty_data_write = {svt_axi_transaction::READONCE};
      bins cleaninvalid_dirty_data_write = {svt_axi_transaction::CLEANINVALID};
      bins cleanshared_dirty_data_write = {svt_axi_transaction::CLEANSHARED};
      bins writeunique_dirty_data_write = {svt_axi_transaction::WRITEUNIQUE};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_lite_coherent_and_ace_snoop_response_association

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association

Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_enable set to 1.

Coverpoints:

coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor.
associate_snoop_xact_for_coh_xact_from_acelite_master: This coverpoint has bins corresponding to valid snoop transactions issued to ACE master for coherent xacts from ACE-Lite Master
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite,associate_snoop_xact_for_coh_xact_from_acelite_master, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_lite_coherent_and_ace_snoop_response_association;
       coh_xact_from_ace_lite: coverpoint ace_lite_coh_xact_type {
    bins readonce_coherent = {svt_axi_transaction::READONCE};
    bins cleanshared_coherent = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins cleaninvalid_coherent = {svt_axi_transaction::CLEANINVALID};
    bins makeinvalid_coherent = {svt_axi_transaction::MAKEINVALID};
    bins writeunique_coherent = {svt_axi_transaction::WRITEUNIQUE};
    bins writelineunique_coherent = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_from_ace: coverpoint snoop_resp_from_ace_master[3:0] {
    bins cresp_0000 = {4'b0000};
    bins cresp_1000 = {4'b1000};
    bins cresp_0001 = {4'b0001};
    bins cresp_1001 = {4'b1001};
    bins cresp_0101 = {4'b0101};
    bins cresp_1101 = {4'b1101};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_wu : coverpoint snoop_resp_from_ace_master[4] {
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_init_cache_state: coverpoint ace_master_init_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_final_cache_state: coverpoint ace_master_final_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     associate_snoop_xact_for_coh_xact_from_acelite_master: coverpoint ace_lite_master_snoop_xact_type {
    bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
    bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
    bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
    bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
    option.weight = 1;
    type_option.weight = 1;
  }
    coh_xact_ace_lite_snp_resp_ace_init_final_cache_state : cross coh_xact_from_ace_lite, associate_snoop_xact_for_coh_xact_from_acelite_master,snoop_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state, ace_final_cache_state {
      ignore_bins ignore_invalid_crresp_ud_sc_sd = binsof(coh_xact_from_ace_lite) intersect {
                                                   svt_axi_transaction::MAKEINVALID ,svt_axi_transaction::WRITELINEUNIQUE} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000 };
    ignore_bins ignore_coherent_snoop_not_possible_combinations = (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::MAKEINVALID} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::MAKEINVALID}) ||
                                                                (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::READONCE} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::READONCE}) ||
                                                                  (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANSHARED}) ||
                                                                   (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::CLEANINVALID} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANINVALID}) ||
                                                                   (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::WRITEUNIQUE} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::CLEANINVALID}) ||
                                                                   (binsof(coh_xact_from_ace_lite) intersect {
                                                                   svt_axi_transaction::WRITELINEUNIQUE} &&
                                                                 !binsof(associate_snoop_xact_for_coh_xact_from_acelite_master) intersect {
                                                                    svt_axi_snoop_transaction::MAKEINVALID});
  ignore_bins ignore_invalid_crresp_cleanshared = binsof(coh_xact_from_ace_lite) intersect {
                                                       svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST} &&
                                                       binsof(snoop_crresp_from_ace) intersect {
                                                       4'b1001,4'b0001};
  ignore_bins ignore_cleanshared_crresp = binsof(coh_xact_from_ace_lite) intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHAREDPERSIST} && binsof(snoop_crresp_from_ace) intersect {4'b1000,4'b1001,4'b1101} && binsof (ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
ignore_bins Ignore_cleanshared_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN}));
ignore_bins ignore_readonce_cleanshared_init_ud_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(ace_init_cache_state) intersect{svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001} || binsof(coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001};
  ignore_bins ignore_readonce_01_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0101} ;
  ignore_bins ignore_cleanshared_init_sd_ud_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} && !binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
     ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coh_xact_from_ace_lite) intersect {
                                                   svt_axi_transaction::WRITEUNIQUE , svt_axi_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000,4'b0101 };
  ignore_bins Ignore_invalid_crresp_readonce = binsof(coh_xact_from_ace_lite) intersect {
                                                     svt_axi_transaction::READONCE} &&
                                                     binsof(snoop_crresp_from_ace) intersect {
                                                      4'b1000};
  ignore_bins ignore_data_transfer_start_cache_state = binsof(snoop_crresp_from_ace) intersect {4'b0001,4'b0101,4'b1101,4'b1001} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_is_shared_end_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b1000,4'b1101,4'b1001} && binsof(ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_pass_dirty_start_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b0101,4'b1101} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
  ignore_bins ignore_wasunique = !binsof(ace_init_cache_state)intersect {svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::UNIQUEDIRTY} && binsof (snoop_crresp_wu) intersect {1} ;
  ignore_bins Ignore_readonce_states = (((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                                ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                                (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                                ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::SHAREDCLEAN}))) ;
   ignore_bins Ignore_cleaninvalid_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ;
  ignore_bins Ignore_makeinvalid_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::MAKEINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ;
  ignore_bins Ignore_writeuniqueorline_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                   (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
   ignore_bins ignore_readonce_final_sc_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDCLEAN}&&binsof(snoop_crresp_from_ace) intersect{4'b1101} ;
  ignore_bins ignore_readonce_final_10_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDDIRTY};
  ignore_bins ignore_readonce_final_sc_10_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY};
  ignore_bins ignore_cleaninvalid_writeunique_init_state = binsof(coh_xact_from_ace_lite)intersect {svt_axi_transaction::CLEANINVALID,svt_axi_transaction::WRITEUNIQUE}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY, svt_axi_snoop_transaction::SHAREDDIRTY} && binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001};
       ignore_bins ignore_invalid_crresp_ud_sc_sd1 = binsof(ace_init_cache_state) intersect {
                                                   svt_axi_snoop_transaction::UNIQUECLEAN ,svt_axi_snoop_transaction::UNIQUEDIRTY} &&
                                                   binsof(snoop_crresp_wu) intersect {
                                                   0 };
     option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id

Covergroup for back to back combination of CLEANINVALID and MAKEINVALID coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id_enable to 1.

Coverpoints:

coh_xact_t1_ace_lite: This coverpoint has bins corresponding to first transaction of a back to back transactions from an ACE-Lite Master
coh_xact_t2_ace_lite: This coverpoint has bins corresponding to second transaction of a back to back transactions from an ACE-Lite Master
snoop_crresp_0_t1 & snoop_crresp_0_t2: This coverpoint has bins for all possible values of CRRESP[0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master.

Cross Coverpoints:

coh_xact_ace_lite_xacts_ace_snp_resp_specific_id: This is the cross-coverage between coh_xact_t1_ace_lite, snoop_crresp_0_t1, coh_xact_t2_ace_lite, snoop_crresp_0_t2, coh_xact_id.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_lite_coherent_and_ace_snoop_response_association_back_to_back_xact_with_specific_id(int specific_id);
      coh_xact_t1_ace_lite: coverpoint ace_lite_coh_xact_t1_type {
      bins writeunique_coherent = {svt_axi_transaction::WRITEUNIQUE};
      bins writelineunique_coherent = {svt_axi_transaction::WRITELINEUNIQUE};
      option.weight = 1;
    }
     coh_xact_t2_ace_lite: coverpoint ace_lite_coh_xact_t2_type {
      bins writeunique_coherent = {svt_axi_transaction::WRITEUNIQUE};
      bins writelineunique_coherent = {svt_axi_transaction::WRITELINEUNIQUE};
      option.weight = 1;
    }
     snoop_crresp_0_t1: coverpoint snoop_resp_t1_from_ace_master[0] {
      bins cresp_0 = {1'b0};
      bins cresp_1 = {1'b1};
      option.weight = 1;
    }
     snoop_crresp_0_t2: coverpoint snoop_resp_t2_from_ace_master[0] {
      bins cresp_0 = {1'b0};
      bins cresp_1 = {1'b1};
      option.weight = 1;
    }
     coh_xact_id : coverpoint ace_lite_coh_xact_id {
      bins ace_lite_xact_id[] = {specific_id};
      option.weight = 1;
    }
     coh_xact_ace_lite_xacts_ace_snp_resp_specific_id : cross coh_xact_t1_ace_lite, snoop_crresp_0_t1, coh_xact_t2_ace_lite, snoop_crresp_0_t2, coh_xact_id {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id

Covergroup: trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id

Covergroup for all coherent transactions generated from ACE-Lite master and the correponding Snoop response from ACE-Masters for these coherent transactions. This will be sampled only when transaction is having configured specific id. This will be a Port Level Covergroup and will be applicable for all ACE-Masters and will only be created when there is atleast one ACE-Lite master in the system. It is constructed and sampled when interface_type is AXI_ACE and trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id_enable set to 1.

Coverpoints:

coh_xact_from_ace_lite: This coverpoint has bins corresponding to each of the valid coherent transactions from an ACE-Lite Master
snp_resp_from_ace: This coverpoint has bins for all possible values of CRRESP[3:0] (Snoop response) that an ACE Master can send for each of the coherent transaction issued from ACE-Lite Master. Since this CG is applicable for only ACE master, it is required to check whether any coherent transaction from ACE-Lite master resulted in this snoop response and subsequently hit bins of coverpoint cmds_from_ace_lite. System Monitor provides this information to Port Monitor.
snoop_crresp_wu: This coverpoint has bins for all possible values of CRRESP[4] (WasUnique)
ace_init_cache_state: This coverpoint has bins for valid initial cache states corresponding to snoops generated by ACE-Master.
ace_final_cache_state: This coverpoint has bins for valid final cache states corresponding to snoops generated by ACE-Master.

Cross Coverpoints:

coh_xact_ace_lite_snp_resp_ace_init_final_cache_state: This is the cross-coverage between coh_xact_from_ace_lite, snp_resp_from_ace, snoop_crresp_wu, ace_init_cache_state and ace_final_cache_state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Table C6-1

covergroup trans_master_ace_lite_coherent_and_ace_snoop_response_association_specific_id;
       coh_xact_from_ace_lite: coverpoint ace_lite_coh_xact_type {
    bins readonce_coherent = {svt_axi_transaction::READONCE};
    bins cleanshared_coherent = {svt_axi_transaction::CLEANSHARED};
      bins coherent_cleansharedpersist_xact = {svt_axi_transaction::CLEANSHAREDPERSIST};
      bins cleaninvalid_coherent = {svt_axi_transaction::CLEANINVALID};
    bins makeinvalid_coherent = {svt_axi_transaction::MAKEINVALID};
    bins writeunique_coherent = {svt_axi_transaction::WRITEUNIQUE};
    bins writelineunique_coherent = {svt_axi_transaction::WRITELINEUNIQUE};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_from_ace: coverpoint snoop_resp_from_ace_master[3:0] {
    bins cresp_0000 = {4'b0000};
    bins cresp_1000 = {4'b1000};
    bins cresp_0001 = {4'b0001};
    bins cresp_1001 = {4'b1001};
    bins cresp_0101 = {4'b0101};
    bins cresp_1101 = {4'b1101};
    option.weight = 1;
    type_option.weight = 1;
  }
     snoop_crresp_wu : coverpoint snoop_resp_from_ace_master[4] {
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_init_cache_state: coverpoint ace_master_init_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     ace_final_cache_state: coverpoint ace_master_final_cache_state {
    bins invalid_cache_state = {svt_axi_snoop_transaction::INVALID};
    bins uniqueclean_cache_state = {svt_axi_snoop_transaction::UNIQUECLEAN};
    bins sharedclean_cache_state = {svt_axi_snoop_transaction::SHAREDCLEAN};
    bins uniquedirty_cache_state = {svt_axi_snoop_transaction::UNIQUEDIRTY};
    bins shareddirty_cache_state = {svt_axi_snoop_transaction::SHAREDDIRTY};
    option.weight = 1;
    type_option.weight = 1;
  }
     coh_xact_ace_lite_snp_resp_ace_init_final_cache_state : cross coh_xact_from_ace_lite, snoop_crresp_from_ace, snoop_crresp_wu, ace_init_cache_state, ace_final_cache_state {
      ignore_bins ignore_invalid_crresp_ud_sc_sd = binsof(coh_xact_from_ace_lite) intersect {
                                                   svt_axi_transaction::MAKEINVALID ,svt_axi_transaction::WRITELINEUNIQUE} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000 };
   ignore_bins Ignore_invalid_rresp_ud_sc_sd = binsof(coh_xact_from_ace_lite) intersect {
                                                   svt_axi_transaction::WRITEUNIQUE , svt_axi_transaction::CLEANINVALID} &&
                                                 !binsof(snoop_crresp_from_ace) intersect {
                                                   4'b0000,4'b0101 };
    ignore_bins ignore_invalid_crresp_cleanshared = binsof(coh_xact_from_ace_lite) intersect {
                                                       svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST} &&
                                                       binsof(snoop_crresp_from_ace) intersect {
                                                       4'b1001,4'b0001};
    ignore_bins Ignore_invalid_crresp_readonce = binsof(coh_xact_from_ace_lite) intersect {
                                                     svt_axi_transaction::READONCE} &&
                                                     binsof(snoop_crresp_from_ace) intersect {
                                                      4'b1000};
  ignore_bins ignore_data_transfer_start_cache_state = binsof(snoop_crresp_from_ace) intersect {4'b0001,4'b0101,4'b1101,4'b1001} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_is_shared_end_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b1000,4'b1101,4'b1001} && binsof(ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
  ignore_bins ignore_pass_dirty_start_cache_state = binsof(snoop_crresp_from_ace) intersect {
                                                         4'b0101,4'b1101} && binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
     ignore_bins ignore_cleanshared_crresp = binsof(coh_xact_from_ace_lite) intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHAREDPERSIST} && binsof(snoop_crresp_from_ace) intersect {4'b1000,4'b1001,4'b1101} && binsof (ace_final_cache_state) intersect {svt_axi_snoop_transaction::INVALID};
    ignore_bins ignore_wasunique = !binsof(ace_init_cache_state)intersect {svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::UNIQUEDIRTY} && binsof (snoop_crresp_wu) intersect {1} ;
  ignore_bins Ignore_readonce_states = (((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                                ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                                (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::UNIQUECLEAN,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                                ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::READONCE}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::SHAREDCLEAN}))) ;
    ignore_bins Ignore_cleanshared_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUECLEAN}) &&
                                               (binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY})) ||
                                               ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANSHARED}) &&
                                               (binsof(ace_init_cache_state) intersect
                                                    {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID,svt_axi_snoop_transaction::SHAREDCLEAN}));
    ignore_bins Ignore_cleaninvalid_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::CLEANINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ;
  ignore_bins Ignore_makeinvalid_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::MAKEINVALID}) &&
                                               (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID})) ;
  ignore_bins Ignore_writeuniqueorline_states = ((binsof(coh_xact_from_ace_lite) intersect
                                                    {svt_axi_transaction::WRITEUNIQUE,
                                                    svt_axi_transaction::WRITELINEUNIQUE}) &&
                                                   (!binsof(ace_final_cache_state) intersect
                                                    {svt_axi_snoop_transaction::INVALID}));
    ignore_bins ignore_readonce_cleanshared_init_ud_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(ace_init_cache_state) intersect{svt_axi_snoop_transaction::UNIQUEDIRTY,svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001} || binsof(coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0000,4'b0001};
    ignore_bins ignore_readonce_final_sc_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDCLEAN}&&binsof(snoop_crresp_from_ace) intersect{4'b1101} ;
    ignore_bins ignore_readonce_01_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE,svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::INVALID}&&binsof(snoop_crresp_from_ace) intersect{4'b0101} ;
    ignore_bins ignore_readonce_final_10_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDDIRTY};
  ignore_bins ignore_readonce_final_sc_10_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::READONCE}&& !binsof(ace_final_cache_state) intersect{svt_axi_snoop_transaction::SHAREDDIRTY,svt_axi_snoop_transaction::UNIQUEDIRTY}&&binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} &&binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY};
    ignore_bins ignore_cleanshared_init_sd_ud_state = binsof (coh_xact_from_ace_lite)intersect {svt_axi_transaction::CLEANSHARED,svt_axi_transaction::CLEANSHAREDPERSIST}&& binsof(snoop_crresp_from_ace) intersect{4'b1000,4'b1001} && !binsof (ace_init_cache_state) intersect {svt_axi_snoop_transaction::SHAREDCLEAN,svt_axi_snoop_transaction::UNIQUECLEAN};
    ignore_bins ignore_cleaninvalid_writeunique_init_state = binsof(coh_xact_from_ace_lite)intersect {svt_axi_transaction::CLEANINVALID,svt_axi_transaction::WRITEUNIQUE}&&binsof(ace_init_cache_state) intersect {svt_axi_snoop_transaction::UNIQUEDIRTY, svt_axi_snoop_transaction::SHAREDDIRTY} && binsof(snoop_crresp_from_ace) intersect {4'b0000,4'b0001};
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_no_cached_copy_overlapping_coherent_xact

Covergroup: trans_master_ace_no_cached_copy_overlapping_coherent_xact

This Covergroup captures no cached copy for overlapping coherant transaction. It is constructed and sampled when interface_type is AXI_ACE and system_ace_no_cached_copy_overlapping_coherent_xact_enable set to 1.

Coverpoints:

no_cached_copy_overlap_coh_xact: This coverpoint has following bins
overlap_readonce_readonce: This bin gets hit when two or more masters issue readonce coherent transactions to overlapping cacheline simultaneously.
overlap_writeunique_writeunique: This bin gets hit when two or more masters issue writeunique coherent transactions to overlapping cacheline simultaneously.
overlap_writelineunique_writelineunique: This bin gets hit when two or more masters issue writelineunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE / ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

covergroup trans_master_ace_no_cached_copy_overlapping_coherent_xact;
     ace_no_cached_copy_overlap_coh_xact: coverpoint no_cached_copy_overlap_coh_xact {
      bins overlap_readonce_readonce = {16'h01_01};
      bins overlap_writeunique_writeunique = {16'h15_15};
      bins overlap_writelineunique_writelineunique = {16'h16_16};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_snoop_and_memory_returns_data

Covergroup: trans_master_ace_snoop_and_memory_returns_data

It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_snoop_and_memory_returns_data_enable set to 1.

Coverpoints:

ace_snoop_and_memory_read_timing: This cover point covers possible relative timings of snoop generation by the interconnect with respect to receiving speculative read data by the interconnect and bin snoop_returns_data_and_memory_not_returns_data covers if a transaction is found with snoop data transfer and without associated slave transaction. The various timings covered are:
- snoop issued before the first read data beat is received through speculative read transaction
- snoop issued after the last beat of read data is received through speculative read transaction
- snoop issued while the read data is being received through speculative read transaction
ace_snoop_and_memory_returns_data_xact_type: Covers the various coherent transaction types for which speculative read was issued. The transaction types covered are READONCE, READCLEAN READNOSHAREDDIRTY, READUNIQUE and READSHARED transactions
At least two ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

covergroup trans_master_ace_snoop_and_memory_returns_data;
     ace_snoop_and_memory_data_timing: coverpoint snoop_and_memory_read_timing {
      bins snoop_data_before_memory_data = {SNOOP_BEFORE_MEMORY_READ};
      bins snoop_data_along_with_memory_data = {SNOOP_ALONG_WITH_MEMORY_READ};
      bins snoop_data_after_memory_data = {SNOOP_AFTER_MEMORY_READ};
      bins snoop_returns_data_and_memory_not_returns_data = {SNOOP_RETURNS_DATA_AND_MEMORY_NOT_RETURNS_DATA};
      option.weight = 1;
    }
     ace_snoop_and_memory_returns_data_xact_type: coverpoint fully_correlated_master_xact.coherent_xact_type {
      bins readonce_snoop_and_memory_returns_data = {svt_axi_transaction::READONCE};
      bins readclean_snoop_and_memory_returns_data = {svt_axi_transaction::READCLEAN};
      bins readnotshreaddirty_snoop_and_memory_returns_data = {svt_axi_transaction::READNOTSHAREDDIRTY};
      bins readunique_snoop_and_memory_returns_data = {svt_axi_transaction::READUNIQUE};
      bins readshared_snoop_and_memory_returns_data = {svt_axi_transaction::READSHARED};
      option.weight = 1;
    }
    snoop_memory_timing_and_xact_cross : cross ace_snoop_and_memory_data_timing, ace_snoop_and_memory_returns_data_xact_type;
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_store_overlapping_coherent_xact

Covergroup: trans_master_ace_store_overlapping_coherent_xact

This Covergroup captures overlapped coherant transaction for readunique and cleanunique . It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_store_overlapping_coherent_xact_enable set to 1.

Coverpoints:

store_overlap_coh_xact: This cover point has follwoing bins
overlap_readunique_readunique: This bin gets hit when two or more masters issue readunique coherent transactions to overlapping cacheline simultaneously.
overlap_cleanunique_cleanunique: This bin gets hit when two or more masters issue cleanunique coherent transactions to overlapping cacheline simultaneously.
overlap_makeunique_makeunique: This bin gets hit when two or more masters issue makeunique coherent transactions to overlapping cacheline simultaneously.

Two or more ACE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C4.10

covergroup trans_master_ace_store_overlapping_coherent_xact;
     ace_store_overlap_coh_xact: coverpoint store_overlap_coh_xact {
      bins overlap_readunique_readunique = {16'h05_05};
      bins overlap_cleanunique_cleanunique = {16'h06_06};
      bins overlap_makeunique_makeunique = {16'h07_07};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_write_during_speculative_fetch

Covergroup: trans_master_ace_write_during_speculative_fetch

It is constructed and sampled when interface_type is AXI_ACE ,interface_category is not AXI_WRITE_ONLY and system_ace_write_during_speculative_fetch_enable set to 1.

Coverpoints:

ace_write_during_speculative_fetch: This cover point covers the following condition: A master issues a read transaction. This results in interconnect generating snoop transactions towards other masters within the domain. The interconnect also generates speculative read transaction for this location. Speculative transaction returns data while the snoop transactions do not return data. The snoop transactions may not return data, either because there is no entry in the snooped masters' caches or a WRITEBACK/WRITECLEAN of dirty data is in progress. The interconnect now detects that a write transaction (the WRITEBACK/WRITECLEAN which is in progress) is received for the same address for which it did a speculative fetch. In such situation, interconnect performs another read from main memory, as originally received data from speculative read is now stale
At least One ACE master needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 6.5.1

covergroup trans_master_ace_write_during_speculative_fetch;
     ace_write_during_speculative_fetch: coverpoint fully_correlated_master_xact.coherent_xact_type {
      bins overlapping_write_during_readonce = {svt_axi_transaction::READONCE};
      bins overlapping_write_during_readclean = {svt_axi_transaction::READCLEAN};
      bins overlapping_write_during_readnotshareddirty = {svt_axi_transaction::READNOTSHAREDDIRTY};
      bins overlapping_write_during_readunique = {svt_axi_transaction::READUNIQUE};
      bins overlapping_write_during_readshared = {svt_axi_transaction::READSHARED};
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier

Covergroup: trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier

It is constructed and sampled when system_ace_xacts_with_high_priority_from_other_master_during_barrier_enable ,barrier_enable and system_monitor_enable set to 1.

Coverpoints:

ace_xacts_with_high_priority_from_other_master_during_barrier: This cover point covers the following condition: When the interconnect receives barrier from a master, then all other transactions launched by other masters in that domain may be stalled. This cover point covers condition where master issues transactions with non-zero QOS value. Then another master issues a barrier transaction within the same domain.
Two or more ACE/ACE_LITE masters needed for this covergroup

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; C 8.1

covergroup trans_master_ace_xacts_with_high_priority_from_other_master_during_barrier;
     ace_xacts_with_high_priority_from_other_master_during_barrier: coverpoint is_xacts_from_other_master_during_barrier_covered {
      bins xacts_from_other_master_during_barrier = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_back_to_back_write_ordering

Covergroup: trans_master_back_to_back_write_ordering

This Covergroup captures back to back write transactions for same id. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is not AXI_READ_ONLY.

Coverpoints:

xact_back_to_back_write_ordering: Captures if back-to-back write transactions with the same id is observed

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

covergroup trans_master_back_to_back_write_ordering @ ( cov_master_back_to_back_write_ordering_event ) ;
     xact_back_to_back_write_ordering: coverpoint back_to_back_write_ordering {
      bins back_to_back_write_with_same_id = {0};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_barrier_id_reuse_for_non_barrier

Covergroup: trans_master_barrier_id_reuse_for_non_barrier

This Covergroup captures number of ID used for barrier transaction and it is reused as normal type. It is constructed when interface_type is AXI_ACE and barrier_enable set to 1.

Coverpoints:

num_barrier_id_reuse_for_non_barrier: Captures the number of times that the ID used for barrier transaction is reused for a normal transaction

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4

covergroup trans_master_barrier_id_reuse_for_non_barrier @ ( cov_barrier_id_reuse_for_non_barrier_event ) ;
     num_barrier_id_reuse_for_non_barrier : coverpoint num_barrier_id_reuse {
      bins barrier_id_reuse = {[1:$]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_coherent_unmatched_excl_access

Covergroup: trans_master_coherent_unmatched_excl_access

This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1.

Coverpoints:

unmatched_excl_access: Captures exclusive load accesses which did not have a corresponding exclusive store access and exclusive store accesses which did not have a corresponding exclusive load access. The unmatched_excl_load_access is hit when a second exclusive load access to the same ID is received before an exclusive store to that ID. The unmatched_excl_store_access is hit when there is no prior exclusive load to an exclusive store (CLEANUNIQUE) transaction.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6

covergroup trans_master_coherent_unmatched_excl_access @ ( cov_coherent_unmatched_excl_access_event ) ;
     unmatched_excl_access : coverpoint coherent_unmatched_excl_access_type {
      bins unmatched_excl_store_access = {0};
      bins unmatched_excl_load_access = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_concurrent_coherent_exclusive_access

Covergroup: trans_master_concurrent_coherent_exclusive_access

This Covergroup captures coherant transactions for exclusive access. It is constructed when interface_type is AXI_ACE and exclusive_access_enable set to 1.

Coverpoints:

num_coherent_exl_access: Number of concurrent coherent exclusive accesses on different IDs

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C9.6

covergroup trans_master_concurrent_coherent_exclusive_access @ ( cov_coherent_exclusive_read_access_event ) ;
     num_coherent_exl_access : coverpoint num_coherent_excl_access_threads {
      bins one_thread = {1};
      bins more_than_one_thread = {[1:$]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_num_outstanding_dvm_syncs_num_dvm_enabled_masters_less_256

Covergroup: trans_master_num_outstanding_dvm_syncs_num_dvm_enabled_masters_less_256

This covergroup captures outstanding dvm based snoop transaction. It is constructed and sampled when svt_axi_port_configuration :: axi_interface_type is AXI_ACE or ACE_LITE svt_axi_port_configuration :: axi_interface_category is !AXI_WRITE_ONLY svt_axi_port_configuration :: dvm_enable = 1 svt_axi_port_monitor_def_cov_data_callback :: num_dvm_enabled_masters <= 256.

Coverpoints:

num_outstanding_dvm_sync_xacts: Captures number of outstanding dvm sync snoop transactions. Note that a master is allowed to send only one outstanding DVM sync transaction (ie, a DVM sync transaction to which a DVM complete is not yet received). Therefore a maximum of 255 outstanding DVM sync snoop transactions is possible only in a system with atleast 256 masters capable of sending DVM transactions.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C12.2

covergroup trans_master_num_outstanding_dvm_syncs_num_dvm_enabled_masters_less_256 @ ( cov_snoop_dvm_sync_event ) ;
     num_outstanding_dvm_sync_xacts : coverpoint num_outstanding_dvm_syncs {
      bins outstanding_dvm_syncs_less_than_256 = {[1:255]};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_num_outstanding_dvm_syncs_num_dvm_enbaled_master_256

Covergroup:trans_master_num_outstanding_dvm_syncs_num_dvm_enbaled_master_256

Coverpoints:

num_outstanding_dvm_sync_xacts: Captures number of outstanding dvm sync snoop transactions. Note that a master is allowed to send only one outstanding DVM sync transaction (ie, a DVM sync transaction to which a DVM complete is not yet received). Therefore a maximum of 256 outstanding DVM sync snoop transactions is possible only in a system with atleast 257 masters capable of sending DVM transactions.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C12.2

covergroup trans_master_num_outstanding_dvm_syncs_num_dvm_enbaled_master_256 @ ( cov_snoop_dvm_sync_event ) ;
     num_outstanding_dvm_sync_xacts : coverpoint num_outstanding_dvm_syncs {
      bins outstanding_dvm_syncs_less_than_256 = {[1:255]};
      bins outstanding_dvm_syncs_equals_256 = {256};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline

Covergroup: trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline

This Covergroup captures snoop rersponse for readunique data transfer. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_resp_datatransfer_with_clean_cacheline: Captures whether data was transferred for READUNIQUE snoop when the cache was in a clean state.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.3.3

covergroup trans_master_readunique_snoop_resp_datatransfer_with_clean_cacheline @ ( cov_readunique_snoop_resp_datatransfer_with_clean_cacheline_event ) ;
     snoop_resp_datatransfer_with_clean_cacheline: coverpoint cov_snoop_item.snoop_resp_datatransfer {
      bins snoop_no_datatransfer = {0};
      bins snoop_with_datatransfer = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr

Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr

This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_xact_type: Captures snoop transactions other than DVM transactions and MAKEINVALID. MAKEINVALID transactions are not captured because it is recommended that MAKEINVALID does not transfer data.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

covergroup trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr;
     snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
      bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
      bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
      bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      option.weight = 1;
   }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite

Covergroup: trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite

This Covergroup captures snoop responses with data transfer when a WRITEUNIQUE or WRITELINEUNIQUE to the same address is in progress, when only one ACE master and one or more ACE_LITE masters present in the system. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE .

Coverpoints:

snoop_xact_type: Captures snoop transactions READONCE,CLEANSHARED,CLEANINVALID. Other transactions are not captured because ACE_LITE master cant fire READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

covergroup trans_master_snoop_data_transfer_during_wu_wlu_to_same_addr_one_ace_acelite;
     snoop_xact_type : coverpoint cov_snoop_item.snoop_xact_type iff(cov_snoop_xact_type_flag){
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      option.weight = 1;
   }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_resp_during_wu_wlu_to_same_addr

Covergroup: trans_master_snoop_resp_during_wu_wlu_to_same_addr

This Covergroup captures snoop response type,WasUnique bit ,awunique value and snoop response with awunique value. It is constructed and sampled when interface_type is AXI_ACE and interface_category is not AXI_READ_ONLY.

Coverpoints:

snoop_crresp: Captures snoop response values
snoop_crresp_wu: Captures value of WasUnique bit in snoop response
awunique_val: Captures the value of signal AWUNIQUE for WRITEUNIQUE and WRITELINEUNIQUE transactions

Cross Coverpoints:

snoop_resp_awunique: Cross of snoop_crresp, snoop_crresp_wu and awunique_val

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C3.1.4

covergroup trans_master_snoop_resp_during_wu_wlu_to_same_addr;
     snoop_crresp : coverpoint cov_crresp[3:0] iff(cov_snoop_resp_flag){
      bins cresp_x0000 = {4'b0000};
      bins cresp_x1000 = {4'b1000};
      bins cresp_x0001 = {4'b0001};
      bins cresp_x1001 = {4'b1001};
      wildcard ignore_bins ig_invalid_cresp1 = {5'b??1?0};
      // WRITEUNIQUE, WRITELINEUNIQUE can be sent only when cache is in clean state
      ignore_bins ignore_pass_dirty = {4'b0101,4'b1101};
      option.weight = 1;
    }
     snoop_crresp_wu : coverpoint cov_crresp[4] iff(cov_snoop_resp_flag){
    bins cresp_wasunique = {1'b1};
    bins cresp_wasnotunique = {1'b0};
    option.weight = 1;
    type_option.weight = 1;
  }
    awunique_val: coverpoint write_xact_to_same_addr_as_snoop.is_unique {
      bins is_not_unique = {0};
      bins is_unique = {1};
      option.weight = 1;
    }
     // When AWUNIQUE is asserted a response that would allow another copy of the cacheline
     // to be created must not be given. So snoop_resp_datatransfer must be low when AWUNIQUE is high
     // So ignore bins that fulfill that condition
     // So ignore bins that fulfill that condition
     //when AWUNIQUE is asserted snooped cache will not be able to retain its copy and will go in shared state .So Snoop
     // response is_shared bit must be driven low
    snoop_resp_awunique : cross snoop_crresp, awunique_val
    {
       ignore_bins ignore_snoop_data_transfer = binsof(snoop_crresp) intersect {4'b1001,4'b0001,4'b1000} && binsof(awunique_val) intersect {1};
       option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_to_same_address_as_read_xact

Covergroup: trans_master_snoop_to_same_address_as_read_xact

This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_WRITE_ONLY.

Coverpoints:

read_xact_to_same_address_as_snoop: Captures read transactions to the same address as a snoop to the master.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C5.2.5

covergroup trans_master_snoop_to_same_address_as_read_xact;
     read_xact_to_same_address_as_snoop: coverpoint read_xact_to_same_address_as_snoop {
      bins coherent_readnosnoop_xact = {0};
      bins coherent_readonce_xact = {1};
      bins coherent_readshared_xact = {2};
      bins coherent_readclean_xact = {3};
      bins coherent_readnotshareddirty_xact = {4};
      bins coherent_readunique_xact = {5};
      bins coherent_cleanunique_xact = {6};
      bins coherent_makeunique_xact = {7};
      bins coherent_cleanshared_xact = {8};
      bins coherent_cleaninvalid_xact = {9};
      bins coherent_makeinvalid_xact = {10};
       bins coherent_cleansharedpersist_xact = {11};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict

Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict

This Covergroup captures read transaction for for same address snooped to master. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY.

Coverpoints:

memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop.
snoop_xact_type: Captures snoop transactions other than DVM transactions
Cross Coverpoints :
trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

covergroup trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict;
       memory_update_excluding_writeevict: coverpoint write_xact_type_to_same_addr_as_snoop {
      bins coherent_writenosnoop_xact = {0};
      bins coherent_writeunique_xact = {1};
      bins coherent_writelineunique_xact = {2};
      bins coherent_writeback_xact = {3};
      bins coherent_writeclean_xact = {4};
      bins coherent_evict_xact = {5};
      option.weight = 1;
      type_option.weight = 1;
    }
     snoop_xact_type : coverpoint cov_snoop_addr_item.snoop_xact_type {
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
      bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
      bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
      bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
      ignore_bins ignore_dvm_snoops = {svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
      option.weight = 1;
      type_option.weight = 1;
    }
    trans_cross_memory_update_snoop_xact_to_same_address : cross memory_update_excluding_writeevict, snoop_xact_type {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite

Covergroup: trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite

This Covergroup captures write transaction for memory update and snoop based dvm unset type. It is constructed and sampled when interface_type is AXI_ACE and interface_catergory is not set to AXI_READ_ONLY. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system.

Coverpoints:

memory_update_excluding_writeevict: Captures WRITEBACK,WRITECLEAN,EVICT,WRITEUNIQUE and WRITELINEUNIQUE transactions to the same address as a snoop. WRITENOSNOOP transactions to non overlapping addresses are captured because WRITENOSNOOP is issued to non-shareable region and another master may not access the same address as that of a WRITENOSNOOP through a snoop.
snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions
Cross Coverpoints :
trans_cross_memory_update_snoop_xact_to_same_address: Crosses memory_update_excluding_writeevict and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

covergroup trans_master_snoop_to_same_addr_as_memory_update_exclude_writeevict_one_ace_acelite;
       memory_update_excluding_writeevict: coverpoint write_xact_type_to_same_addr_as_snoop {
      bins coherent_writenosnoop_xact = {0};
      bins coherent_writeunique_xact = {1};
      bins coherent_writelineunique_xact = {2};
      bins coherent_writeback_xact = {3};
      bins coherent_writeclean_xact = {4};
      bins coherent_evict_xact = {5};
      option.weight = 1;
      type_option.weight = 1;
    }
     snoop_xact_type : coverpoint cov_snoop_addr_item.snoop_xact_type {
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
      ignore_bins ignore_dvm_snoops = {svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
      option.weight = 1;
      type_option.weight = 1;
    }
    trans_cross_memory_update_snoop_xact_to_same_address : cross memory_update_excluding_writeevict, snoop_xact_type {
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_to_same_addr_as_writeevict

Covergroup: trans_master_snoop_to_same_addr_as_writeevict

This Covergroup captures write transaction for same address as snoop and snoop transaction except dvm based. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. Coverpoints:

write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop.
snoop_xact_type: Captures snoop transactions other than DVM transactions

Cross Coverpoints :

trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

covergroup trans_master_snoop_to_same_addr_as_writeevict;
     write_evict_xact: coverpoint write_xact_type_to_same_addr_as_snoop {
      bins coherent_writeevict_xact = {6};
      option.weight = 1;
    }
     snoop_xact_type : coverpoint cov_snoop_addr_item.snoop_xact_type {
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_readshared_xact = {svt_axi_snoop_transaction::READSHARED};
      bins snoop_readclean_xact = {svt_axi_snoop_transaction::READCLEAN};
      bins snoop_readnotshareddirty_xact = {svt_axi_snoop_transaction::READNOTSHAREDDIRTY};
      bins snoop_readunique_xact = {svt_axi_snoop_transaction::READUNIQUE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
      ignore_bins ignore_dvm_snoops = {svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
      option.weight = 1;
      type_option.weight = 1;
    }
    trans_cross_writeevict_snoop_xact_to_same_address : cross write_evict_xact, snoop_xact_type {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite

Covergroup: trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite

This Covergroup captures write evict and snoop xact transaction. It is constructed and sampled when interface_type is AXI_ACE ,interface_category is AXI_READ_WRITE writeevict_enable set to 1. This covergroup will be created when there is only one ACE-master and minimum one or more than one ACE_LITE master in the system.

Coverpoints:

write_evict_xact: Captures WRITEEVICT transactions to the same address as a snoop.
snoop_xact_type:Coverpoint of svt_axi_snoop_transaction :: snoop_xact_type for READONCE,CLEANSHARED,CLEANINVALID and MAKEINVALID snoop transactions recieved on master port . This excludes READSHARED,READCLEAN,READNOTSHAREDDIRTY,READUNIQUE,DVMMESSAGE,DVMCOMPLETE transactions

Cross Coverpoints :

trans_cross_writeevict_snoop_xact_to_same_address: Crosses write_evict_xact and snoop_xact_type

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C6.6.1

covergroup trans_master_snoop_to_same_addr_as_writeevict_one_ace_acelite;
     write_evict_xact: coverpoint write_xact_type_to_same_addr_as_snoop {
      bins coherent_writeevict_xact = {6};
      option.weight = 1;
    }
     snoop_xact_type : coverpoint cov_snoop_addr_item.snoop_xact_type {
      bins snoop_readonce_xact = {svt_axi_snoop_transaction::READONCE};
      bins snoop_cleanshared_xact = {svt_axi_snoop_transaction::CLEANSHARED};
      bins snoop_cleaninvalid_xact = {svt_axi_snoop_transaction::CLEANINVALID};
      bins snoop_makeinvalid_xact = {svt_axi_snoop_transaction::MAKEINVALID};
      ignore_bins ignore_dvm_snoops = {svt_axi_snoop_transaction::DVMMESSAGE,svt_axi_snoop_transaction::DVMCOMPLETE};
      option.weight = 1;
      type_option.weight = 1;
    }
    trans_cross_writeevict_snoop_xact_to_same_address : cross write_evict_xact, snoop_xact_type {
      option.weight = 0;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_master_write_after_read_ordering

Covergroup: trans_master_write_after_read_ordering

This Covergroup captures write transaction after read happens. It is constructed when port_kind is AXI_MASTER and interface_type is not AXI4_STREAM & interface_category is AXI_READ_WRITE.

Coverpoints:

xact_write_after_read_ordering: Captures the order of completion of a write transaction issued after a read

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C1.3.4

covergroup trans_master_write_after_read_ordering @ ( cov_master_write_after_read_ordering_event ) ;
     xact_write_after_read_ordering : coverpoint write_after_read_ordering {
      bins write_after_read_with_write_completing_first = {0};
      bins write_after_read_with_read_completing_first = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_meta_axi_read

Covergroup: trans_meta_axi_read

This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for read address, and read data channels. It is constructed and sampled when interface type is not AXI_WRITE_ONLY & trans_meta_axi_read_enable is asserted.

Coverpoints:

ARVALID_to_ARREADY_Delay: Captures min, mid and max range of delays between signals arvalid and arready
RVALID_to_RREADY_Delay: Captures min, mid and max range of delays between signals rvalid and rready
ARVALID_to_prev_ARVALID_Delay: Captures min, mid and max range of delays between current and previous arvalid signals
RVALID_to_prev_RVALID_Delay: Captures min, mid and max range of delays between current and previous rvalid signals
ARVALID_to_first_RVALID_Delay: Captures min, mid and max range of delays between arvalid and first rvalid signals
ARVALID_before_ARREADY: Captures if ARVALID signal comes before ARREADY signal
ARREADY_before_ARVALID: Captures if ARREADY signal comes before ARVALID signal
RVALID_before_RREADY: Captures if RVALID signal comes before RREADY signal
RREADY_before_RVALID: Captures if RREADY signal comes before RVALID signal

covergroup trans_meta_axi_read;
     option.per_instance = 1;
    ARVALID_to_ARREADY_Delay : coverpoint cov_ARVALID_to_ARREADY_Delay {
      bins arvalid_to_arready_delay_min = {0};
      bins arvalid_to_arready_delay_mid = {[1:( 16/2)]};
      bins arvalid_to_arready_delay_max = {[( 16/2)+1:$]};
    }
    RVALID_to_RREADY_Delay : coverpoint cov_RVALID_to_RREADY_Delay {
      bins rvalid_to_rready_delay_min = {0};
      bins rvalid_to_rready_delay_mid = {[1:( 16/2)]};
      bins rvalid_to_rready_delay_max = {[( 16/2)+1:$]};
    }
    ARVALID_to_prev_ARVALID_Delay : coverpoint cov_ARVALID_to_prev_ARVALID_Delay {
      bins arvalid_to_prev_arvalid_delay_min = {1};
      bins arvalid_to_prev_arvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins arvalid_to_prev_arvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    RVALID_to_prev_RVALID_Delay : coverpoint cov_RVALID_to_prev_RVALID_Delay {
      bins rvalid_to_prev_rvalid_delay_min = {1};
      bins rvalid_to_prev_rvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins rvalid_to_prev_rvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    ARVALID_to_first_RVALID_Delay : coverpoint cov_ARVALID_to_first_RVALID_Delay {
      bins arvalid_to_first_rvalid_delay_min = {[0:1]};
      bins arvalid_to_first_rvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins arvalid_to_first_rvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
    }
    ARVALID_before_ARREADY: coverpoint cov_ARVALID_before_ARREADY {
      bins arvalid_before_arready = {1};
    }
    ARREADY_before_ARVALID: coverpoint cov_ARREADY_before_ARVALID {
      bins arready_before_arvalid = {1};
    }
    RVALID_before_RREADY: coverpoint cov_RVALID_before_RREADY {
      bins rvalid_before_rready = {1};
    }
    RREADY_before_RVALID: coverpoint cov_RREADY_before_RVALID {
      bins rready_before_rvalid = {1};
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_meta_axi_write

Covergroup: trans_meta_axi_write

This Covergroup captures delay and predelay scenarios for handshake between valid and ready signal for write address, write data,write response channels It is constructed sampled when interface type is not AXI_READ_ONLY & trans_meta_axi_write_enable is asserted.

Coverpoints:

AWVALID_to_AWREADY_Delay: Captures min, mid and max range of delays between signals awvalid and awready
WVALID_to_WREADY_Delay: Captures min, mid and max range of delays between signals wvalid and wready
BVALID_to_BWREADY_Delay: Captures min, mid and max range of delays between signals bvalid and bready
AWVALID_to_prev_AWVALID_Delay: Captures min, mid and max range of delays between current and previous awvalid signals
WVALID_to_prev_WVALID_Delay: Captures min, mid and max range of delays between current and previous wvalid signals
AWVALID_to_first_WVALID_Delay: Captures min, mid and max range of delays between awvalid and first wvalid signals
last_wdata_handshake_to_BVALID_Delay: Captures min, mid and max range of delays between last write data handshake to bvalid signals
AWVALID_before_AWREADY: Captures if AWVALID signal comes before AWREADY signal
AWREADY_before_AWVALID: Captures if AWREADY signal comes before AWVALID signal
BVALID_before_BREADY: Captures if BVALID signal comes before BREADY signal
BREADY_before_BVALID: Captures if BREADY signal comes before BVALID signal
WVALID_before_WREADY: Captures if WVALID signal comes before WREADY signal
WREADY_before_WVALID: Captures if WREADY signal comes before WVALID signal or WREADY,WVALID signals are comes at same time
AWVALID_before_WREADY: Captures if AWVALID signal comes before WREADY signal
WREADY_before_AWVALID: Captures if WREADY signal comes before AWVALID signal
AWREADY_before_WVALID: Captures if AWREADY signal comes before WVALID signal
WVALID_before_AWREADY: Captures if WVALID signal comes before AWREADY signal
AWVALID_before_WVALID: Captures if AWVALID signal comes before WVALID signal
WVALID_before_AWVALID: Captures if WVALID signal comes before AWVALID signal

covergroup trans_meta_axi_write;
     option.per_instance = 1;
    AWVALID_to_AWREADY_Delay : coverpoint cov_AWVALID_to_AWREADY_Delay {
      bins awvalid_to_awready_delay_min = {0};
      bins awvalid_to_awready_delay_mid = {[1:( 16/2)]};
      bins awvalid_to_awready_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    WVALID_to_WREADY_Delay : coverpoint cov_WVALID_to_WREADY_Delay {
      bins wvalid_to_wready_delay_min = {0};
      bins wvalid_to_wready_delay_mid = {[1:( 16/2)]};
      bins wvalid_to_wready_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    BVALID_to_BREADY_Delay : coverpoint cov_BVALID_to_BREADY_Delay {
      bins bvalid_to_bready_delay_min = {0};
      bins bvalid_to_bready_delay_mid = {[1:( 16/2)]};
      bins bvalid_to_bready_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    AWVALID_to_prev_AWVALID_Delay : coverpoint cov_AWVALID_to_prev_AWVALID_Delay {
      bins awvalid_to_prev_awvalid_delay_min = {1};
      bins awvalid_to_prev_awvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins awvalid_to_prev_awvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
      option.at_least = 1;
    }
    WVALID_to_prev_WVALID_Delay : coverpoint cov_WVALID_to_prev_WVALID_Delay {
      bins wvalid_to_prev_wvalid_delay_min = {1};
      bins wvalid_to_prev_wvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins wvalid_to_prev_wvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
      option.at_least = 1;
    }
    AWVALID_to_first_WVALID_Delay : coverpoint cov_AWVALID_to_first_WVALID_Delay {
      bins awvalid_to_first_wvalid_delay_min = {0};
      bins awvalid_to_first_wvalid_delay_mid = {[1:(( 16 + 16)/2)]};
      bins awvalid_to_first_wvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
      option.at_least = 1;
    }
    last_wdata_handshake_to_BVALID_Delay : coverpoint cov_last_wdata_handshake_to_BVALID_Delay {
      bins last_wdata_handshake_to_bvalid_delay_min = {1};
      bins last_wdata_handshake_to_bvalid_delay_mid = {[2:( 16/2)]};
      bins last_wdata_handshake_to_bvalid_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    AWVALID_before_AWREADY :coverpoint cov_AWVALID_before_AWREADY {
      bins awvalid_before_awready = {1};
      option.at_least = 3;
    }
    AWREADY_before_AWVALID :coverpoint cov_AWREADY_before_AWVALID {
      bins awready_before_awvalid = {1};
      option.at_least = 3;
    }
    BVALID_before_BREADY :coverpoint cov_BVALID_before_BREADY {
      bins bvalid_before_bready = {1};
      option.at_least = 3;
    }
    BREADY_before_BVALID :coverpoint cov_BREADY_before_BVALID {
      bins bready_before_bvalid = {1};
      option.at_least = 3;
    }
    WVALID_before_WREADY : coverpoint cov_WVALID_before_WREADY {
      bins wvalid_before_wready = {1};
      option.at_least = 3;
    }
    WREADY_before_WVALID : coverpoint cov_WREADY_before_WVALID {
      bins wready_before_wvalid = {1};
      option.at_least = 3;
    }
    AWVALID_before_WREADY : coverpoint cov_AWVALID_before_WREADY{
      bins awvalid_before_wready = {1};
      option.at_least = 3;
    }
    WREADY_before_AWVALID : coverpoint cov_WREADY_before_AWVALID{
      bins wready_before_awvalid = {1};
      option.at_least = 3;
    }
    AWREADY_before_WVALID : coverpoint cov_AWREADY_before_WVALID{
      bins awready_before_wvalid = {1};
      option.at_least = 3;
    }
    WVALID_before_AWREADY : coverpoint cov_WVALID_before_AWREADY{
      bins wvalid_before_awready = {1};
      option.at_least = 3;
    }
    AWVALID_before_WVALID : coverpoint cov_AWVALID_before_WVALID{
      bins awvalid_before_wvalid = {1};
      option.at_least = 3;
    }
    WVALID_before_AWVALID : coverpoint cov_WVALID_before_AWVALID{
      bins wvalid_before_awvalid = {1};
      option.at_least = 3;
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_meta_axi4_stream

Covergroup: trans_meta_axi4_stream

This Covergroup captures delay scenarios for tvalid and tready for AXI4_STREAM. It is constructed and sampled when interface type is AXI4_STREAM & trans_meta_axi4_stream_enable is asserted.

Coverpoints:

TVALID_to_TREADY_Delay: Captures min, mid and max range of delays between signals tvalid and tready
TVALID_to_prev_TVALID_Delay: Captures min, mid and max range of delays between current and previous tvalid signals
TVALID_before_TREADY: Captures if TVALID signal comes before TREADY signal
TREADY_before_TVALID: Captures if TREADY signal comes before TVALID signal

covergroup trans_meta_axi4_stream;
     option.per_instance = 1;
    TVALID_to_TREADY_Delay : coverpoint cov_TVALID_to_TREADY_Delay {
      bins tvalid_to_tready_delay_min = {0};
      bins tvalid_to_tready_delay_mid = {[1:( 16/2)]};
      bins tvalid_to_tready_delay_max = {[( 16/2)+1:$]};
      option.at_least = 1;
    }
    TVALID_to_prev_TVALID_Delay : coverpoint cov_TVALID_to_prev_TVALID_Delay {
      bins tvalid_to_prev_tvalid_delay_min = {1};
      bins tvalid_to_prev_tvalid_delay_mid = {[2:(( 16 + 16)/2)]};
      bins tvalid_to_prev_tvalid_delay_max = {[(( 16 + 16)/2)+1:$]};
      option.at_least = 1;
    }
    TVALID_before_TREADY : coverpoint cov_TVALID_before_TREADY {
      bins tvalid_before_tready = {1};
      option.at_least = 1;
    }
    TREADY_before_TVALID : coverpoint cov_TREADY_before_TVALID {
      bins tready_before_tvalid = {1};
      option.at_least = 1;
    }
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_non_barrier_xact_after_256_outstanding_barrier_xact

Covergroup: trans_non_barrier_xact_after_256_outstanding_barrier_xact

This Covergroup captures barrier outstanding transaction. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_non_barrier_xact_after_256_outstanding_barrier_xact_enable & barrier enable set to 1.

Coverpoints:

non_barrier_after_256_outstanding_barrier_xact: Captures if active transactions on write channel occur after 256 barrier outstanding transactions are accepted by slave component

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.2

covergroup trans_non_barrier_xact_after_256_outstanding_barrier_xact @ ( cov_non_barrier_after_256_outstanding_barrier_sample_event ) ;
     non_barrier_after_256_outstanding_barrier_xact : coverpoint non_barrier_after_256_outstanding_barrier{
      bins write_xact_after_256_outstanding_barrier_xact = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_outstanding_read_with_same_id_to_different_slaves

Covergroup: trans_outstanding_read_with_same_id_to_different_slaves

This Covergroup captures outstanding read request having same id for different slaves. This covergroup is constructed for all master interface types except AXI4_STREAM and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1.

Coverpoints:

axi_outstanding_read_with_same_id_to_different_slaves: This is covered when:
- A master issues two outstanding read transactions with the same ID
- These read transactions are targeted to two different slaves

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613

covergroup trans_outstanding_read_with_same_id_to_different_slaves @ ( cov_outstanding_read_with_same_id_to_different_slaves_sample_event ) ;
     axi_outstanding_read_with_same_id_to_different_slaves: coverpoint outstanding_read_with_same_id_to_different_slaves {
      bins outstanding_with_same_id_to_different_slaves = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_outstanding_write_with_same_id_to_different_slaves

Covergroup: trans_outstanding_write_with_same_id_to_different_slaves

This Covergroup captures outstanding write request having same id for different slaves. This covergroup is constructed for all master interface types and only if the number of slaves in the system (svt_axi_system_configuration :: num_slaves) is greater than 1 and trans_outstanding_read_with_same_id_to_different_slaves_enable set to 1.

Coverpoints:

axi_outstanding_read_with_same_id_to_different_slaves: This is covered when:
- A master issues two outstanding write transactions with the same ID
- These write transactions are targeted to two different slaves

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613

covergroup trans_outstanding_write_with_same_id_to_different_slaves @ ( cov_outstanding_write_with_same_id_to_different_slaves_sample_event ) ;
     axi_outstanding_write_with_same_id_to_different_slaves: coverpoint outstanding_write_with_same_id_to_different_slaves {
      bins outstanding_with_same_id_to_different_slaves = {1};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_xact_domain_after_innershareable_barrier

Covergroup: trans_xact_domain_after_innershareable_barrier

This Covergroup captures innershareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_innershareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_innershareable_barrier: This is covered when:
- Master initiates inner-shareable transaction followed by inner-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with none/outer/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

covergroup trans_xact_domain_after_innershareable_barrier @ ( cov_xact_domain_after_innershareable_barrier_sample_event ) ;
     axi_xact_domain_after_innershareable_barrier: coverpoint xact_domain_after_innershareable_barrier {
      bins innershareable_read_barrier_followed_by_nonshareable_read_xact = {0};
      bins innershareable_read_barrier_followed_by_outershareable_read_xact = {2};
      bins innershareable_read_barrier_followed_by_systemshareable_read_xact = {3};
      bins innershareable_write_barrier_followed_by_nonshareable_write_xact = {4};
      bins innershareable_write_barrier_followed_by_outershareable_write_xact = {6};
      bins innershareable_write_barrier_followed_by_systemshareable_write_xact = {7};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_xact_domain_after_nonshareable_barrier

Covergroup: trans_xact_domain_after_nonshareable_barrier

This Covergroup captures nonshareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_nonshareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_nonshareable_barrier: This is covered when:
- Master initiates non-shareable transaction followed by non-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with inner/outer/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

covergroup trans_xact_domain_after_nonshareable_barrier @ ( cov_xact_domain_after_nonshareable_barrier_sample_event ) ;
     axi_xact_domain_after_nonshareable_barrier: coverpoint xact_domain_after_nonshareable_barrier {
      bins nonshareable_read_barrier_followed_by_innershareable_read_xact = {1};
      bins nonshareable_read_barrier_followed_by_outershareable_read_xact = {2};
      bins nonshareable_read_barrier_followed_by_systemshareable_read_xact = {3};
      bins nonshareable_write_barrier_followed_by_innershareable_write_xact = {5};
      bins nonshareable_write_barrier_followed_by_outershareable_write_xact = {6};
      bins nonshareable_write_barrier_followed_by_systemshareable_write_xact = {7};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_xact_domain_after_outershareable_barrier

Covergroup: trans_xact_domain_after_outershareable_barrier

This Covergroup captures outershareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_outershareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_outershareable_barrier: This is covered when:
- Master initiates outer-shareable transaction followed by outer-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with none/inner/system domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

covergroup trans_xact_domain_after_outershareable_barrier @ ( cov_xact_domain_after_outershareable_barrier_sample_event ) ;
     axi_xact_domain_after_outershareable_barrier: coverpoint xact_domain_after_outershareable_barrier {
      bins outershareable_read_barrier_followed_by_nonshareable_read_xact = {0};
      bins outershareable_read_barrier_followed_by_innershareable_read_xact = {1};
      bins outershareable_read_barrier_followed_by_systemshareable_read_xact = {3};
      bins outershareable_write_barrier_followed_by_nonshareable_write_xact = {4};
      bins outershareable_write_barrier_followed_by_innershareable_write_xact = {5};
      bins outershareable_write_barrier_followed_by_systemshareable_write_xact = {7};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_xact_domain_after_systemshareable_barrier

Covergroup: trans_xact_domain_after_systemshareable_barrier

This Covergroup captures systemshareable read and write barrier request after master issues shareable transactions type. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_domain_after_systemshareable_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_domain_after_aftershareable_barrier: This is covered when:
- Master initiates system-shareable transaction followed by outer-shareable read/write barrier pairs
- Before the barrier completes, the same master initiates any other coherent transactions with inner/outer/systemnone domains

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.2.2

covergroup trans_xact_domain_after_systemshareable_barrier @ ( cov_xact_domain_after_systemshareable_barrier_sample_event ) ;
     axi_xact_domain_after_systemshareable_barrier: coverpoint xact_domain_after_systemshareable_barrier {
      bins systemshareable_read_barrier_followed_by_nonshareable_read_xact = {0};
      bins systemshareable_read_barrier_followed_by_innershareable_read_xact = {1};
      bins systemshareable_read_barrier_followed_by_outershareable_read_xact = {2};
      bins systemshareable_write_barrier_followed_by_nonshareable_write_xact = {4};
      bins systemshareable_write_barrier_followed_by_innershareable_write_xact = {5};
      bins systemshareable_write_barrier_followed_by_outershareable_write_xact = {6};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

covergroup
svt_axi_port_monitor_def_cov_callback::trans_xact_ordering_after_barrier

Covergroup: trans_xact_ordering_after_barrier

This Covergroup captures read & write transaction ordering for barrier response scenarios. It is constructed when interface type is AXI_ACE or ACE_LITE and trans_xact_ordering_after_barrier_enable & barrier enable set to 1.

Coverpoints:

axi_xact_ordering_after_barrier: This is covered when a master issues transactions between issuing a barrier transaction on the address channel and receiving the read and write barrier responses.
- Such transactions have no ordering guarantee with respect to the barrier. On the address channel, these transactions are permitted to remain after the barrier transaction or they are permitted to overtake the barrier transaction.

Reference: AMBA AXI and ACE Protocol Specification: ARM IHI 0022E ID022613; Section C8.4.1

covergroup trans_xact_ordering_after_barrier @ ( cov_xact_ordering_after_barrier_sample_event ) ;
     axi_xact_ordering_after_barrier: coverpoint xact_ordering_after_barrier {
      bins read_xact_overtake_barrier_response = {0};
      bins read_xact_fallbehind_barrier_response = {1};
      bins write_xact_overtake_barrier_response = {2};
      bins write_xact_fallbehind_barrier_response = {3};
      option.weight = 1;
    }
    option.per_instance = 1;
    endgroup

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svt_axi_port_monitor_def_cov_callback Class Reference

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